Integrated circuit and method of forming the same

1. A method of forming an integrated circuit, the method comprising:

generating, by a processor, a first standard cell layout design of the integrated circuit, the generating the first standard cell layout design includes:

generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width in a second direction different from the first direction, and the first standard cell layout design having a first height in the second direction;

generating a second standard cell layout design of the integrated circuit, the generating the second standard cell layout design includes:

generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width in the second direction different from the first width, and the second standard cell layout design having a second height in the second direction different from the first height, and the second standard cell layout design being adjacent to the first standard cell layout design; and

manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design.

2. The method of claim 1 , wherein

each pin layout pattern of the first set of pin layout patterns is separated from an adjacent pin layout pattern of the first set of pin layout patterns in the second direction by a first pitch; and

each pin layout pattern of the second set of pin layout patterns is separated from an adjacent pin layout pattern of the second set of pin layout patterns in the second direction by a second pitch different from the first pitch.

3. The method of claim 1 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns having a first size, and being placed on the first set of pin layout patterns; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of pin layout patterns having a second size different from the first size, and being placed on the second set of pin layout patterns.

4. The method of claim 3 , wherein

the first size includes at least a first via pattern width or a first via pattern height; and

the second size includes at least a second via pattern width different from the first via pattern width, or a second via pattern height different from the first via pattern height.

5. The method of claim 1 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures, the first set of conductive feature layout patterns extending in the second direction, overlapping at least the first set of pin layout patterns, and being on a second layout level different from the first layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures, the second set of conductive feature layout patterns extending in the second direction, overlapping at least the second set of pin layout patterns, and being on the second layout level.

6. The method of claim 5 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a third set of conductive feature layout patterns corresponding to fabricating a third set of conductive structures, the third set of conductive feature layout patterns extending in the first direction, overlapping at least the first set of conductive feature layout patterns, and being on a third layout level different from the first layout level and the second layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a fourth set of conductive feature layout patterns corresponding to fabricating a fourth set of conductive structures, the fourth set of conductive feature layout patterns extending in the first direction, overlapping at least the second set of conductive feature layout patterns, and being on the third layout level.

7. The method of claim 6 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns having a first size, and being placed between the first set of conductive feature layout patterns and the third set of conductive feature layout patterns; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of via layout patterns having a second size, and being placed between the second set of conductive feature layout patterns and the fourth set of conductive feature layout patterns.

8. The method of claim 7 , wherein

the first size includes at least a first via pattern width or a first via pattern height; and

the second size includes at least a second via pattern width different from the first via pattern width, or a second via pattern height different from the first via pattern height.

9. The method of claim 6 , wherein

each conductive feature layout pattern of the third set of conductive feature layout patterns is separated from an adjacent conductive feature layout pattern of the third set of conductive feature layout patterns in the second direction by a first pitch; and

each conductive feature layout pattern of the fourth set of conductive feature layout patterns is separated from an adjacent conductive feature layout pattern of the fourth set of conductive feature layout patterns in the second direction by a second pitch different from the first pitch.

10. The method of claim 1 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of active region layout patterns corresponding to fabricating a first set of active regions, the first set of active region layout patterns having a third width in the second direction, and being placed on a second layout level different from the first layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of active region layout patterns corresponding to fabricating a second set of active regions, the second set of active region layout patterns having a fourth width in the second direction different from the third width, and being placed on the second layout level.

11. An integrated circuit comprising:

a first region of the integrated circuit comprising:

a first set of active regions in a substrate, the first set of active regions extending in a first direction and having a first width in a second direction different from the first direction; and

a first set of pins extending in the first direction, being over the first set of active regions, and having a second width in the second direction,

wherein the first region has a first height in the second direction; and

a second region of the integrated circuit adjacent to the first region, the second region comprising:

a second set of active regions in the substrate, the second set of active regions extending in the first direction and having a third width in the second direction different from the first width; and

a second set of pins extending in the first direction, being over the second set of active regions, and having a fourth width in the second direction different from the second width,

wherein the second region has a second height in the second direction different from the first height, and

the first set of pins and the second set of pins are in a first metal layer of the integrated circuit.

12. The integrated circuit of claim 11 , wherein

the first region of the integrated circuit further comprises:

a first set of conductive structures extending in the second direction, and overlapping at least the first set of pins, the first set of conductive structures being on a second metal layer different from the first metal layer; and

a first set of vias between the first set of pins and the first set of conductive structures, the first set of vias having a first via width and a first via height; and the second region of the integrated circuit further comprises:

a second set of conductive structures extending in the second direction, and overlapping at least the second set of pins, the second set of conductive structures being on the second metal layer; and

a second set of vias between the second set of pins and the second set of conductive structures, the second set of vias having a second via width different from the first via width or a second via height different from the first via height.

13. The integrated circuit of claim 12 , wherein

the first region of the integrated circuit further comprises:

a third set of conductive structures extending in the first direction, and overlapping at least the first set of conductive structures, the third set of conductive structures being on a third metal layer different from the first metal layer and the second metal layer, each of the third set of conductive structures is separated from an adjacent conductive structure of the third set of conductive structures in the second direction by a first pitch; and

a third set of vias between the first set of conductive structures and the third set of conductive structures, and the third set of vias having a third via width and a third via height; and

the second region of the integrated circuit further comprises:

a fourth set of conductive structures extending in the first direction, and overlapping at least the second set of conductive structures, the fourth set of conductive structures being on the third metal layer, each of the fourth set of conductive structures is separated from an adjacent conductive structure of the fourth set of conductive structures in the second direction by a second pitch different from the first pitch; and

a fourth set of vias between the second set of conductive structures and the fourth set of conductive structures, and the fourth set of vias having a fourth via width different from the third via width or a fourth via height different from the third via height.

14. The integrated circuit of claim 11 , wherein

the first set of active regions includes a first number of fins;

the second set of active regions includes a second number of fins different from the first number of fins;

each of the first set of pins is separated from an adjacent pin of the first set of pins in the second direction by a first pitch; and

each of the second set of pins is separated from an adjacent pin of the second set of pins in the second direction by a second pitch different from the first pitch.

15. A method of forming an integrated circuit, the method comprising:

generating, by a processor, a first standard cell layout design of the integrated circuit, the generating the first standard cell layout design includes:

generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width in a second direction different from the first direction, and the first standard cell layout design having a first height in the second direction; and

generating a first via layout pattern corresponding to fabricating a first via, the first via layout pattern having a first via height in the second direction, and being over a first pin of the first set of pin layout patterns; and

generating a second standard cell layout design of the integrated circuit, the second standard cell layout design having a second height in the second direction different from the first height, and the second standard cell layout design being adjacent to the first standard cell layout design, the generating the second standard cell layout design includes:

generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width in the second direction, the second width being greater than the first width; and

generating a second via layout pattern corresponding to fabricating a second via, the second via layout pattern having a second via height in the second direction, the second via height being greater than the first via height, and being over the second set of pin layout patterns; and

manufacturing the integrated circuit based on at least the first standard cell layout design or the second standard cell layout design.

16. The method of claim 15 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of active region layout patterns corresponding to fabricating a first set of active regions, the first set of active region layout patterns having a third width in the second direction, and being on a second layout level different from the first layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of active region layout patterns corresponding to fabricating a second set of active regions, the second set of active region layout patterns having a fourth width in the second direction greater than the third width, and being on the second layout level.

17. The method of claim 16 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of conductive feature layout patterns corresponding to fabricating a first set of conductive structures, the first set of conductive feature layout patterns extending in the second direction, overlapping at least the first set of pin layout patterns, and being on a third layout level different from the first layout level and the second layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of conductive feature layout patterns corresponding to fabricating a second set of conductive structures, the second set of conductive feature layout patterns extending in the second direction, overlapping at least the second set of pin layout patterns, and being on the third layout level.

18. The method of claim 17 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a third set of conductive feature layout patterns corresponding to fabricating a third set of conductive structures, the third set of conductive feature layout patterns extending in the first direction, overlapping at least the first set of conductive feature layout patterns, and being on a fourth layout level different from the first layout level, the second layout level and the third layout level; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a fourth set of conductive feature layout patterns corresponding to fabricating a fourth set of conductive structures, the fourth set of conductive feature layout patterns extending in the first direction, overlapping at least the second set of conductive feature layout patterns, and being on the fourth layout level.

19. The method of claim 18 , wherein

the generating the first standard cell layout design of the integrated circuit, further includes:

generating a first set of via layout patterns corresponding to fabricating a first set of vias, the first set of via layout patterns having a first size, and being between the first set of conductive feature layout patterns and the third set of conductive feature layout patterns; and

the generating the second standard cell layout design of the integrated circuit, further includes:

generating a second set of via layout patterns corresponding to fabricating a second set of vias, the second set of via layout patterns having a second size, and being between the second set of conductive feature layout patterns and the fourth set of conductive feature layout patterns.

20. The method of claim 19 , wherein

the first size includes at least a first via pattern width or a first via pattern height;

the second size includes at least a second via pattern width different from the first via pattern width, or a second via pattern height different from the first via pattern height;

each pin layout pattern of the first set of pin layout patterns is separated from an adjacent pin layout pattern of the first set of pin layout patterns in the second direction by a first pitch; and

each pin layout pattern of the second set of pin layout patterns is separated from an adjacent pin layout pattern of the second set of pin layout patterns in the second direction by a second pitch different from the first pitch.