ENHANCED PROCESSOR FUNCTIONS FOR CALCULATION
Enhanced processor functions for calculation are described. An example of an apparatus includes one or more processors including one or more processing resources and a memory to store data, the data including data for compute operations. A processing resource of the one or more processing resources includes a configurable pipeline for calculation operations, and wherein the configurable pipeline may be utilized to perform both a normal instruction for a calculation in a certain precision and a systolic instruction for a calculation in a certain precision.
1 . An apparatus comprising:
one or more processors including one or more processing resources; and
a memory to store data, the data including data for compute operations;
wherein a processing resource of the one or more processing resources includes a configurable pipeline for calculation operations, and wherein the configurable pipeline may be utilized to perform both:
a normal instruction for a calculation in a certain precision; and
a systolic instruction for a calculation in a certain precision.
2 . The apparatus of claim 1 , wherein a precision for calculation is double precision floating point (FP64).
3 . The apparatus of claim 1 , wherein a calculation is performed utilizing the configurable pipeline for a machine learning operation.
4 . The apparatus of claim 1 , further comprising a decoder, the decoder to decode an instruction and determine whether the decoded instruction is a regular instruction or a systolic instruction based on an ISA (instruction set architecture) emitted by a compiler.
5 . The apparatus of claim 4 , further comprising a register file, the register file to receive the decoded instruction.
6 . The apparatus of claim 5 , wherein the register file is further to receive a result of the instruction from the configurable pipeline.
7 . The apparatus of claim 5 , wherein the register file is a general register file (GRF).
8 . The apparatus of claim 1 , wherein the one or more processors include a graphics processor.
9 . A method comprising:
receiving an instruction for processing, the instruction requiring processing of a calculation at a certain precision;
decoding the instruction, wherein decoding includes determining whether the instruction is a non-systolic instruction for a calculation in the certain precision or a systolic instruction for a calculation in the certain precision;
configuring a configurable pipeline to provide either non-systolic or systolic calculation;
providing data for processing; and
receiving a result of the non-systolic or systolic calculation.
10 . The method of claim 9 , wherein a precision for calculation is double precision floating point (FP64).
11 . The method of claim 9 , wherein the instruction requires calculation for a machine learning training or inference operation.
12 . The method of claim 9 , wherein decoding includes determining whether the is a regular instruction or a systolic instruction based on an ISA (instruction set architecture) emitted by a compiler.
13 . The method of claim 12 , further comprising receiving the decoded instruction at a register file.
14 . The method of claim 13 , further comprising receiving a result of the instruction from the configurable pipeline at the register file.
15 . A system comprising:
one or more processors including a graphics processor, the graphics processor including one or more processing resources;
a memory to store data, the data including data for compute operations;
a decoder to decode instructions; and
a register file to receive the decoded instructions;
wherein a processing resource of the one or more processing resources includes a configurable pipeline for calculation operations, and wherein the configurable pipeline may be utilized to perform both:
a normal instruction for a calculation in a certain precision; and
a systolic instruction for a calculation in a certain precision.
16 . The system of claim 15 , wherein a precision for calculation is one include half precision floating point (FP16), single precision floating point (FP32), or double precision floating point (FP64).
17 . The system of claim 15 , wherein a calculation is performed utilizing the configurable pipeline for a machine learning operation.
18 . The system of claim 15 , wherein the decoder is to determine whether a decoded instruction is a regular instruction or a systolic instruction based on an ISA (instruction set architecture) emitted by a compiler.
19 . The system of claim 15 , wherein the register file is further to receive a result of the instruction from the configurable pipeline.
20 . The system of claim 15 , wherein the register file is a general register file (GRF).