Systems and methods for systolic array design from a high-level program
Systems and methods for automated systolic array design from a high-level program are disclosed. One implementation of a systolic array design supporting a convolutional neural network includes a two-dimensional array of reconfigurable processing elements arranged in rows and columns. Each processing element has an associated SIMD vector and is connected through a local connection to at least one other processing element. An input feature map buffer having a double buffer is configured to store input feature maps, and an interconnect system is configured to pass data to neighboring processing elements in accordance with a processing element scheduler. A CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.
1. A systolic array supporting a convolutional neural network (CNN), comprising:
a two-dimensional array of reconfigurable processing elements arranged in rows and columns, each processing element having an associated single instruction multiple data (SIMD) vector and being connected through a local connection to at least one other processing element;
an input feature map buffer having a double buffer for storing input feature maps;
an interconnect system to pass data to neighboring processing elements in accordance with a processing element scheduler, and wherein
a CNN computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.
2. The systolic array of claim 1 , wherein the CNN computation is defined in a high-level C program, and wherein the mapping is performed from the high-level C program to an FPGA bitstream.
3. The systolic array of claim 1 , wherein a processing element includes a digital signal processor (DSP) block or a vector processor consisting of multiple DSP blocks.
4. The systolic array of claim 1 , wherein a processing element implements mathematical operations that include addition, subtraction, multiplication, and division, and wherein the processing element includes lookup tables.
5. The systolic array of claim 1 , wherein the double buffer is comprised of a first buffer and a second buffer, wherein in a first data cycle the first buffer is configured to store data fetched by the systolic array from an external memory, wherein in the first data cycle the second buffer is configured to feed the data into a processing element, wherein in a second data cycle the second buffer is configured to store data fetched by the systolic array from an external memory, and wherein in the second data cycle the first buffer is configured to feed the data into a processing element.
6. The systolic array of claim 5 , wherein each of the first buffer and the second buffer is comprised of an array of buffer segments, and wherein each buffer segment is coupled to a neighboring buffer segment via a local connection.
7. The systolic array of claim 1 , wherein the CNN computation includes multiple nested loops.
8. The systolic array of claim 1 , wherein the interconnect system defines bi-directional connections between reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements in adjacent columns of the columns.
9. The systolic array of claim 8 , wherein the interconnect system defines one directional connections between reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements in adjacent rows of the rows.
10. The systolic array of claim 1 , wherein the processing element scheduler is configured to implement timing protocols defining when each processing element passes data to a neighboring process element or receives data from a neighboring process element over the interconnect system.
11. The systolic array of claim 1 , wherein the processing element scheduler is configured to control synchronization of data in the two-dimensional array of reconfigurable processing elements to implement pipelining between neighboring reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements.
12. The systolic array of claim 1 , wherein the processing element scheduler is configured to control synchronization of data in the two-dimensional array of reconfigurable processing elements to implement data reuse between neighboring reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements.
13. The systolic array of claim 1 , wherein the interconnect system implements multiple parallel channels between neighboring reconfigurable processing elements of the two- dimensional array of reconfigurable processing elements.
14. A systolic array, comprising:
a two-dimensional array of reconfigurable processing elements arranged in rows and columns, each processing element having an associated single instruction multiple data (SIMD) vector and each being connected to adjacent reconfigurable processing elements of the two-dimensional array;
an input feature map buffer having a double buffer for storing input feature maps;
an interconnect system to pass data to neighboring processing elements in accordance with a processing element scheduler, and wherein
a computation is mapped onto the two-dimensional array of reconfigurable processing elements using an automated system configured to determine suitable reconfigurable processing element parameters.
15. The systolic array of claim 14 , wherein the double buffer is comprised of a first buffer and a second buffer, wherein in a first data cycle the first buffer is configured to store data fetched by the systolic array from an external memory, wherein in the first data cycle the second buffer is configured to feed the data into a processing element, wherein in a second data cycle the second buffer is configured to store data fetched by the systolic array from an external memory, and wherein in the second data cycle the first buffer is configured to feed the data into a processing element.
16. The systolic array of claim 14 , wherein the interconnect system defines bi-directional connections between reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements in adjacent columns of the columns and one directional connections between reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements in adjacent rows of the rows.
17. The systolic array of claim 14 , wherein the processing element scheduler is configured to implement timing protocols defining when each processing element passes data to a neighboring process element or receives data from a neighboring process element over the interconnect system.
18. The systolic array of claim 14 , wherein the processing element scheduler is configured to control synchronization of data in the two-dimensional array of reconfigurable processing elements to implement pipelining between neighboring reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements.
19. The systolic array of claim 14 , wherein the processing element scheduler is configured to control synchronization of data in the two-dimensional array of reconfigurable processing elements to implement data reuse between neighboring reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements.
20. The systolic array of claim 1 , wherein the interconnect system implements multiple parallel channels between neighboring reconfigurable processing elements of the two-dimensional array of reconfigurable processing elements.