High performance multi-dimensional device and logic integration

1. A semiconductor device, comprising:

a bottom substrate;

a device plane over the bottom substrate, the device plane including at least a first layer of semiconductor devices;

a dielectric layer over the device plane;

localized substrates over the dielectric layer, the localized substrates separated from each other along a top surface of the bottom substrate, wherein at least two of the localized substrates comprise different semiconductor materials; and

a second layer of semiconductor devices over the localized substrates.

2. The semiconductor device of claim 1 , wherein the dielectric layer comprises a recess filled by a corresponding localized substrate.

3. The semiconductor device of claim 1 , wherein the localized substrates are crystalline.

4. The semiconductor device of claim 1 , wherein the localized substrates comprise at least one of silicon or germanium.

5. The semiconductor device of claim 4 , wherein the second layer of semiconductor devices comprises an n-type metal-oxide-semiconductor (NMOS) over a localized silicon substrate and a p-type metal-oxide-semiconductor (PMOS) over a localized germanium substrate.

6. A method of microfabrication, the method comprising:

forming a device plane over a bottom substrate, the device plane including at least a first layer of semiconductor devices;

forming a dielectric layer over the device plane;

forming a target layer over the dielectric layer, the target layer including localized regions that are separated from each other along a top surface of the bottom substrate, wherein at least two of the localized substrates comprise different semiconductor materials, wherein the target layer extends in a direction parallel to a working surface of the bottom substrate, and the localized regions extend in the direction; and

forming a second layer of semiconductor devices over the localized regions of the target layer.

7. The method of claim 6 , further comprising forming recesses in the dielectric layer so that the target layer fills the recesses.

8. The method of claim 7 , further comprising removing a portion of the target layer over the dielectric layer so that the remaining portion of the target layer is in the recesses.

9. The method of claim 6 , further comprising performing a thermal process to increase crystallinity of the localized regions of the target layer.

10. The method of claim 9 , wherein the thermal process comprises metal crystal annealing.

11. The method of claim 10 , prior to performing the thermal process, further comprising:

forming a patterned seed layer on the target layer, the patterned seed layer including localized seed regions on the localized regions of the target layer.

12. The method of claim 11 , wherein the localized seed regions have at least one geometric shape that directs crystallization of the localized regions of the target layer to a predetermined crystal orientation during the metal crystal annealing.

13. The method of claim 9 , wherein the thermal process comprises laser annealing.

14. The method of claim 13 , prior to forming the target layer, further comprising:

forming a cap layer over the bottom substrate; and

forming recesses in the cap layer so that the target layer fills the recesses.

15. The method of claim 9 , wherein:

the thermal process makes the localized regions of the target layer crystalline; and

the crystalline localized regions of the target layer function as localized substrates for the second layer of semiconductor devices.

16. The method of claim 9 , prior to performing the thermal process, further comprising doping the localized regions of the target layer.