Forming a cavity with a wet etch for backside contact formation
In some embodiments, the present disclosure relates to an integrated chip that includes a channel structure extending between a first source/drain region and a second source/drain region. Further, a gate electrode is arranged directly over the channel structures, and an upper interconnect contact is arranged over and coupled to the gate electrode. A backside contact is arranged below and coupled to the first source/drain region. The backside contact has a width that decreases from a bottommost surface of the backside contact to a topmost surface of the backside contact.
1. An integrated chip comprising:
a channel structure extending between a first source/drain region and a second source/drain region;
a gate electrode arranged directly over the channel structure;
an upper interconnect contact arranged over and coupled to the gate electrode; and
a backside contact arranged below and coupled to the first source/drain region,
wherein the backside contact has a width that continuously decreases as its measured at different heights from a bottommost surface of the backside contact to a topmost surface of the backside contact; and
wherein the upper interconnect contact has a width that increases from a bottommost surface of the upper interconnect contact to a topmost surface of the upper interconnect contact.
2. The integrated chip of claim 1 , wherein the channel structure comprises multiple nanosheet channel structures spaced apart from one another by the gate electrode.
3. The integrated chip of claim 1 , wherein the backside contact is arranged in a lower interconnect dielectric structure, and wherein the channel structure comprises a fin structure, wherein the fin structure continuously extends between the lower interconnect dielectric structure and the gate electrode.
4. The integrated chip of claim 1 , wherein the backside contact has outermost sidewalls that are substantially planar.
5. The integrated chip of claim 1 , wherein the backside contact has outermost sidewalls that are substantially curved.
6. The integrated chip of claim 1 , further comprising:
an additional backside contact arranged below and coupled to the second source/drain region,
wherein the additional backside contact has a width that decreases from a bottommost surface of the additional backside contact to a topmost surface of the additional backside contact.
7. An integrated chip comprising:
a channel structure extending between a first source/drain region and a second source/drain region;
a gate electrode arranged directly over the channel structure;
an upper interconnect contact arranged over and coupled to the gate electrode; and
a first backside contact arranged below and coupled to the first source/drain region,
wherein a bottommost surface of the first backside contact has a first width, wherein a topmost surface of the first backside contact has a second width, wherein the first width is a maximum width of the first backside contact, wherein the second width is a minimum width of the first backside contact;
wherein the first width transitions to the second width to form first sidewalls;
wherein the transition comprises a continuous increase in width of the first backside contact beginning from the topmost surface of the first backside contact and ending at the bottommost surface of the first backside contact.
8. The integrated chip of claim 7 , wherein the channel structure comprises multiple nanosheet channel structures, and wherein the gate electrode is arranged between upper and lower surfaces of each nanosheet channel structure.
9. The integrated chip of claim 7 , further comprising:
a lower interconnect dielectric structure, wherein the first backside contact is arranged within the lower interconnect dielectric structure.
10. The integrated chip of claim 9 , further comprising:
a second backside contact arranged below and coupled to the second source/drain region, wherein the second backside contact is spaced apart from the first backside contact by the lower interconnect dielectric structure.
11. The integrated chip of claim 7 , wherein the first source/drain region has a bottommost surface with a third width, and wherein the third width is substantially equal to the second width.
12. The integrated chip of claim 7 , wherein the channel structure.
13. The integrated chip of claim 7 , wherein the first sidewalls have a substantially curved profile along a length of the first sidewalls, the length extending between the topmost and bottommost surfaces of the first backside contact.
14. The integrated chip of claim 7 , wherein the channel structure has an upper surface which extends between the first source/drain region and the second source/drain region and which is co-planar with upper surfaces of the first source/drain region and the second source/drain region.
15. A method comprising: forming a first dummy gate structure and a second dummy gate structure over a frontside of a substrate;
performing a first removal process to form a trench by removing portions of the substrate according to the first and second dummy gate structures, wherein the trench defines a first channel structure underlying the first dummy gate structure and a second channel structure underlying the second dummy gate structure;
performing a second removal process to form a cavity within the substrate, wherein the cavity is arranged below the first and second channel structures, wherein the cavity has a first width that is greater than a second width of the trench, wherein the first width is a maximum width of the cavity, and wherein the second width is a maximum width of the trench;
forming a dummy material within the cavity;
forming a source/drain region within the trench;
replacing the first and second dummy gate structures with first and second gate electrodes, respectively;
forming an upper interconnect structure over the first and second gate electrodes;
thinning a backside of the substrate to expose the dummy material within the cavity; and
replacing the dummy material with a conductive material to form a backside contact coupled to the source/drain region,
wherein the backside contact has a maximum width that is less than or equal to the first width of the cavity.
16. The method of claim 15 , further comprising:
forming a continuous protection layer over the first and second dummy gate structures, over the frontside of the substrate, and along outer sidewalls of the first and second channel structures; and
performing a third removal process to remove portions of the continuous protection layer arranged on the frontside of the substrate, thereby forming a protection layer on outer sidewalls of the first and second channel structures,
wherein the protection layer is formed between the first and second removal processes, and wherein the protection layer is substantially resistant to removal by the second removal process.
17. The method of claim 16 , wherein a bottommost surface of the cavity is defined by an etch stop layer arranged within the substrate.
18. The method of claim 15 , further comprising:
bonding a carrier substrate to the upper interconnect structure after forming the upper interconnect structure and before thinning a backside of the substrate.
19. The method of claim 15 , wherein the second removal process comprises a wet etchant that removes portions of the substrate in vertical and horizontal directions.
20. The method of claim 19 , wherein the wet etchant comprises hydrofluoric acid or ammonium hydroxide.