Flat metal features for microelectronics applications
Advanced flat metals for microelectronics are provided. While conventional processes create large damascene features that have a dishing defect that causes failure in bonded devices, example systems and methods described herein create large damascene features that are planar. In an implementation, an annealing process creates large grains or large metallic crystals of copper in large damascene cavities, while a thinner layer of copper over the field of a substrate anneals into smaller grains of copper. The large grains of copper in the damascene cavities resist dishing defects during chemical-mechanical planarization (CMP), resulting in very flat damascene features. In an implementation, layers of resist and layers of a second coating material may be applied in various ways to resist dishing during chemical-mechanical planarization (CMP), resulting in very flat damascene features.
1. An apparatus comprising:
a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, the first conductive layer-filled cavity having a first width of at least 5 microns and a first depth that is less than the first width; and
a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein the second conductive layer-filled cavity has a second width and a second depth that is less than the second width and wherein a width of a grain size of a conductor within the second conductive layer-filled cavity is more than 5% of the width of one of (i) the first conductive layer-filled cavity or (ii) the second conductive layer-filled cavity
wherein the first bonding surface is bonded to the second bonding surface.
2. The apparatus of claim 1 , further comprising:
a first barrier layer over a surface of the first conductive layer-filled cavity; and
a second barrier layer over a surface of the second conductive layer-filled cavity.
3. The apparatus of claim 1 , wherein:
the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and
the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species.
4. The apparatus of claim 1 , wherein the first depth is between about 1 to 7 microns and the second depth is between about 1 to about 7 microns.
5. The apparatus of claim 1 , wherein the first bonding surface is bonded to the second bonding surface via a hybrid bond direct bond.
6. The apparatus of claim 1 , wherein the first width of the first is 2 to 5 times the second width.
7. The apparatus of claim 1 , wherein:
the first bonding surface comprise a first flat conductive metal feature having a width of at least 5 microns on the first substrate, wherein a dishing concavity across the width of the first flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the first flat conductive metal feature; and
the second bonding surface comprise a second flat conductive metal feature having a width of at least 5 microns on the second substrate, wherein a dishing concavity across the width of the second flat conductive metal feature has a maximum dishing depth of less than 10 nanometers for each micron (nm/μ) of depth of the second flat conductive metal feature.
8. The apparatus of claim 7 , wherein the first flat conductive metal feature and the second flat conductive metal feature are from a group consisting of:
a flat conductive metal feature with a width of at least 10 microns (μm) and a maximum dishing of less than 10 nanometers (nm);
a flat conductive metal feature with a width of at least 10 μm and a maximum dishing of less than 10 nanometers per micron (nm/μm) of depth of the flat conductive metal feature; and
a bonded metallic feature larger than 10 μm.
9. The apparatus of claim 7 , wherein the width of the first flat conductive metal feature and the width the second flat conductive metal feature are more than 25 microns and the dishing concavity of the first flat conductive metal feature and the second flat conductive metal feature are each less than 10 nanometers.
10. The apparatus of claim 7 , wherein the width of the first flat conductive metal feature and the width of the second flat conductive metal feature are each between 26-150 microns and the dishing concavity of the first flat conductive metal feature and the width of the second flat conductive metal feature are each less than 20 nanometers.
11. The apparatus of claim 1 , wherein at least one of the first substrate or the second substrate comprise a microelectronic device.
12. An apparatus comprising:
a first substrate comprising a first bonding surface that comprises a first conductive layer-filled cavity, wherein a conductive layer of the first conductive layer-filled cavity has a width of at least 10 microns, wherein a grain size of a conductor within the first conductive layer-filled cavity is more than 5% of the width of the first conductive layer-filled cavity; and
a second substrate comprising a second bonding surface that comprises a second conductive layer-filled cavity, wherein a width of a conductive layer of the second conductive layer-filled cavity is 2-10 times the width of the conductive layer of the first conductive layer filled cavity,
wherein the first bonding surface is bonded to the second bonding surface.
13. The apparatus of claim 12 , further comprising:
a first barrier layer over a surface of the first conductive layer-filled cavity; and
a second barrier layer over a surface of the second conductive layer-filled cavity.
14. The apparatus of claim 12 , wherein:
the first bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species; and
the second bonding surface comprises one of a nitrogen atomic species, a fluoride atomic species, or a boron atomic species.
15. The apparatus of claim 12 , wherein at least one of the first substrate or the second substrate comprise a microelectronic device.