3D memory circuit
Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets. The z-axis connections in some embodiments electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data between the third set of data lines on the third IC die and the first and second set of data lines of the first and second of memory block sets on the first and second IC dies. These z-axis connections between the dies are very short as the dies are very thin. For instance, in some embodiments, the z-axis connections are less than 10 or 20 microns. The z-axis connections are through silicon vias (TSVs) in some embodiments.
1. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first plurality of memory blocks with a first set of data lines;
a second IC die stacked on top of the first IC die and comprising a second plurality of memory blocks with a second set of data lines;
a third IC die stacked on top of the first and second IC dies and comprising a third set of data lines;
a plurality of z-axis connections that connect the third set of data lines with the first and second sets of data lines to carry data to and from the first and second plurality of memory blocks when data is being written to, and read from, the first and second plurality of memory blocks, wherein a first z-axis connection of the plurality of z-axis connections extends through the second IC die in a z direction perpendicular to the second IC die and is coupled to a data line of the first set of data lines and a data line of the third set of data lines; and
a set of memory circuits, comprising:
a first individually addressable memory circuit comprising the first plurality of memory blocks,
a second individually addressable memory circuit comprising the second plurality of memory blocks;
a set of addressing circuits to activate different addressed locations in first and second pluralities of memory blocks; and
a set of input/output (I/O) circuits to write/read data to addressed locations in the first and second pluralities of memory blocks, the I/O circuit set comprising the third set of data lines.
2. The 3D circuit of claim 1 , wherein the addressing circuit set includes a set of sense amplifiers defined on the first and second IC dies.
3. The 3D circuit of claim 2 , wherein the I/O circuit set comprises buffers defined on the third IC die.
4. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first plurality of memory blocks with a first set of data lines;
a second IC die stacked on top of the first IC die and comprising a second plurality of memory blocks with a second set of data lines;
a third IC die stacked on top of the first and second IC dies and comprising a third set of data lines;
a plurality of z-axis connections that connect the third set of data lines with the first and second sets of data lines to carry data to and from the first and second plurality of memory blocks when data is being written to, and read from, the first and second plurality of memory blocks, wherein a first z-axis connection of the plurality of z-axis connections extends through the second IC die in a z direction perpendicular to the second IC die and is coupled to a data line of the first set of data lines and a data line of the third set of data lines; and
a set of one or more memory circuits, comprising:
the first and second plurality of memory blocks;
a set of addressing circuits to activate different addressed locations in the first and second plurality of memory blocks; and
a set of input/output (I/O) circuits to write/read data to addressed locations in the first and second plurality of memory blocks, the I/O circuit set comprising the third set of data lines, wherein
the addressing circuit set includes a set of sense amplifiers defined on the first and second IC dies, and
the I/O circuit set comprises level shifters defined on the third IC die.
5. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first plurality of memory blocks with a first set of data lines;
a second IC die stacked on top of the first IC die and comprising a second plurality of memory blocks with a second set of data lines;
a third IC die stacked on top of the first and second IC dies and comprising a third set of data lines;
a plurality of z-axis connections that connect the third set of data lines with the first and second sets of data lines to carry data to and from the first and second plurality of memory blocks when data is being written to, and read from, the first and second plurality of memory blocks, wherein a first z-axis connection of the plurality of z-axis connections extends through the second IC die in a z direction perpendicular to the second IC die and is coupled to a data line of the first set of data lines and a data line of the third set of data lines; and
a set of one or more memory circuits, comprising:
the first and second plurality of memory blocks;
a set of addressing circuits to activate different addressed locations in the first and second plurality of memory blocks; and
a set of input/output (I/O) circuits to write/read data to addressed locations in the first and second plurality of memory blocks, the I/O circuit set comprising the third set of data lines, wherein
the addressing circuit set includes a set of sense amplifiers defined on the first and second IC dies, and
the I/O circuit set comprises stateful storage circuits defined on the third IC die, the stateful storage circuits comprising one of latches and flip flops.
6. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first plurality of memory blocks with a first set of data lines;
a second IC die stacked on top of the first IC die and comprising a second plurality of memory blocks with a second set of data lines;
a third IC die stacked on top of the first and second IC dies and comprising a third set of data lines;
a plurality of z-axis connections that connect the third set of data lines with the first and second sets of data lines to carry data to and from the first and second plurality of memory blocks when data is being written to, and read from, the first and second plurality of memory blocks, wherein a first z-axis connection of the plurality of z-axis connections extends through the second IC die in a z direction perpendicular to the second IC die and is coupled to a data line of the first set of data lines and a data line of the third set of data lines; and
a set of one or more memory circuits, comprising:
the first and second plurality of memory blocks;
a set of addressing circuits to activate different addressed locations in the first and second plurality of memory blocks; and
a set of input/output (I/O) circuits to write/read data to addressed locations in the first and second plurality of memory blocks, the I/O circuit set comprising the third set of data lines, wherein
the addressing circuit set includes a set of sense amplifiers defined on the first and second IC dies, and
the third IC die comprises a plurality of compute circuits that receive through the third set of data lines the data that is read from the memory circuit set.
7. The 3D circuit of claim 6 , wherein the compute circuits are processing cores for performing calculations associated with neurons of a neural network.
8. A three-dimensional (3D) circuit comprising:
a first integrated circuit (IC) die comprising a first plurality of memory blocks with a first set of data lines;
a second IC die stacked on top of the first IC die and comprising a second plurality of memory blocks with a second set of data lines;
a third IC die stacked on top of the first and second IC dies and comprising a third set of data lines; and
a plurality of z-axis connections that connect the third set of data lines with the first and second sets of data lines to carry data to and from the first and second plurality of memory blocks when data is being written to, and read from, the first and second plurality of memory blocks, wherein
a first z-axis connection of the plurality of z-axis connections extends through the second IC die in a z direction perpendicular to the second IC die and is coupled to a data line of the first set of data lines and a data line of the third set of data lines, and
the plurality of z-axis connections electrically connect circuit nodes in overlapping portions of the first and third IC dies, and overlapping portions of second and third IC dies, in order to carry data to and from the third set of data lines on the third IC die from and to the first and second sets of data lines of the first and second plurality of memory blocks on the first and second IC dies.
9. The 3D circuit of claim 8 further comprising:
a first plurality of bit lines on the first IC die connected to (i) storage cells of the first plurality of memory blocks, and (ii) the first set of data lines; and
a second plurality of bit lines on the second IC die connected to (i) storage cells of the second plurality of memory blocks, and (ii) the second set of data lines.
10. The 3D circuit of claim 8 , wherein each of a subset of z-axis connections is shorter than 10 microns.
11. The 3D circuit of claim 8 , wherein each of a subset of z-axis connections is shorter than 5 microns.
12. The 3D circuit of claim 1 , wherein the first and second plurality of memory blocks are DRAM memory blocks.
13. The 3D circuit of claim 7 , wherein each of a plurality of DRAM memory blocks comprises single cell, single transistor storage cells.
14. The 3D circuit of claim 1 , further comprising:
a substrate on which the 3D circuit is mounted.