Semiconductor device having an upper epitaxial layer contacting two lower epitaxial layers

1. A semiconductor device, comprising:

a first source/drain epitaxial layer disposed at a source/drain region of a first fin structure;

a second source/drain epitaxial layer disposed at a source/drain region of a second fin structure;

an etch-stop layer covering part of the first and second source/drain epitaxial layers; and

a third source/drain epitaxial layer disposed on the first and second epitaxial layers and disposed on an upper portion of the etch-stop layer disposed between the first source/drain epitaxial layer and the second source/drain epitaxial layer.

2. The semiconductor device of claim 1 , wherein the third source/drain epitaxial layer is disposed in recesses formed in the first and second source/drain epitaxial layers.

3. The semiconductor device of claim 1 , further comprising a conductive contact disposed on the third source/drain epitaxial layer.

4. The semiconductor device of claim 3 , further comprising a silicide layer disposed between the third source/drain epitaxial layer and the conductive contact.

5. The semiconductor device of claim 4 , wherein the silicide layer includes titanium silicide.

6. The semiconductor device of claim 1 , wherein the third source/drain epitaxial layer has a different composition than the first and second source/drain epitaxial layers.

7. The semiconductor device of claim 6 , wherein:

the first, second and third source/drain epitaxial layers contain germanium, and

a concentration of germanium in the third source/drain epitaxial layer is higher than a concentration of germanium in the first and second source/drain epitaxial layers.

8. A semiconductor device, comprising:

a first fin field effect transistor (FinFET) including a first gate structure disposed over first channel regions of two first fin structures, a first source/drain epitaxial layer disposed at a first source/drain region of each of the two first fin structures, and a first etch-stop layer covering part of the first source/drain structure;

a second FinFET including a second gate structure disposed over second channel regions of two second fin structures, a second source/drain epitaxial layer disposed at a second source/drain region of each of the two second fin structures, and a second etch-stop layer covering part of the second source/drain structure, wherein:

the first FinFET further includes a third source/drain epitaxial layer disposed on the first source/drain epitaxial layer of one of the two first fin structures and the first source/drain epitaxial layer of another of the two first fin structures, and disposed on an upper portion of the first etch-stop layer, and

the second FinFET further includes a fourth source/drain epitaxial layer disposed on the second source/drain epitaxial layer of one of the two second fin structures and the second source/drain epitaxial layer of another of the two second fin structures, and disposed on an upper portion of the second etch-stop layer.

9. The semiconductor device of claim 8 , wherein the first FinFET is a first conductivity-type and the second FinFET is a second conductive type.

10. The semiconductor device of claim 9 , wherein:

the second conductivity type is p-type,

the second and third source/drain epitaxial layers contain germanium, and

a concentration of germanium in the third source/drain epitaxial layer is higher than a concentration of germanium in the second source/drain epitaxial layer.

11. The semiconductor device of claim 10 , wherein:

at least one of the second and third source/drain epitaxial layers further contains boron.

12. The semiconductor device of claim 11 , wherein a concentration of boron is in a range from 1.0×10 20 cm −3 to 6.0×10 21 cm −3 .

13. The semiconductor device of claim 10 , wherein:

the second epitaxial layer includes Si 1-x Ge x and the third epitaxial layer includes Si 1-y Ge y , and

0.15≤x≤0.8, 0.2≤y≤1.0 andx<y.

14. The semiconductor device of claim 9 , wherein:

the first conductivity type is n-type, and

the first epitaxial layer includes one selected from the group consisting of SiP, InP and GaInP.

15. The semiconductor device of claim 14 , wherein a concentration of phosphorous in the first epitaxial layer is in a range from 1.0×10 20 cm −3 to 6.0×10 21 cm 3 .

16. A semiconductor device, comprising:

a gate structure disposed over a first channel region of a first fin structure and a second channel region of a second fin structure;

a first epitaxial layer disposed at a first source/drain region of the first fin structure;

a second epitaxial layer disposed at a second source/drain region of the second fin structure;

a third epitaxial layer; and

a dielectric layer made of silicon nitride and covering part of the first and second source/drain epitaxial layers, wherein:

a bottom of the third epitaxial layer is disposed on and in direct contact with upper portions of the dielectric layer and on the first and second epitaxial layers.

17. The semiconductor device of claim 16 , further comprising a conductive contact disposed on the third epitaxial layer.

18. The semiconductor device of claim 17 , further comprising a silicide layer disposed between the third epitaxial layer and the conductive contact.

19. The semiconductor device of claim 18 , wherein the conductive contact includes an adhesive layer and a main metal layer made of a different material than the adhesive layer.

20. The semiconductor device of claim 19 , wherein the adhesive layer is in contact with the third epitaxial layer.