3D memory semiconductor devices and structures
A 3D memory device, the device including: a plurality of memory cells, where each of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source and a drain; a plurality of bit-line pillars, where each of the plurality of bit-line pillars is directly connected to a plurality of the source or the drain, where each of the plurality of bit-line pillars includes metal atoms such that the plurality of bit-line pillars have at least partial metallic properties; and a thermal path from the bit-line pillars to an external surface of the device to remove heat. Various 3D processing flows and methods are also disclosed.
1. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source and a drain;
a plurality of bit-line pillars,
wherein each of said plurality of bit-line pillars is directly connected to a plurality of said source or said drain,
wherein each of said plurality of bit-line pillars comprises metal atoms such that said plurality of bit-line pillars have at least partial metallic properties; and
a thermal path from said bit-line pillars to an external surface of said device to remove heat.
2. The device according to claim 1 ,
wherein each of said plurality of memory cells comprises a charge trap memory and a poly-silicon channel, and
wherein said metal atoms enable hot electron programming of said charge trap memory.
3. The device according to claim 1 ,
wherein said 3D memory comprises a NOR or an AND memory architecture.
4. The device according to claim 1 ,
wherein said plurality of memory cells comprise a metalized source or drain.
5. The device according to claim 1 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
6. The device according to claim 1 ,
wherein each of said at least one memory transistor comprises a channel,
wherein said channel comprises crystallized polysilicon, and
wherein said crystallized polysilicon has been crystallized from a heat sourced from said source or drain of said channel.
7. The device according to claim 1 ,
wherein at least one of said memory transistor is self-aligned to an overlaying memory transistor.
8. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source and a drain;
a plurality of bit-line pillars,
wherein each of said bit-line pillars is directly connected to a plurality of said source or said drain; and
a thermal path from said bit-line pillars to an external surface of said device to remove heat.
9. The device according to claim 8 ,
wherein each of said plurality of bit-line pillars comprise metal atoms such that said plurality of bit-line pillars have at least partial metallic properties.
10. The device according to claim 8 ,
wherein said 3D memory comprises a NOR or an AND memory architecture.
11. The device according to claim 8 ,
wherein said plurality of memory cells comprise a metalized source or drain.
12. The device according to claim 8 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
13. The device according to claim 8 ,
wherein each of said at least one memory transistor comprises a channel,
wherein said channel comprises crystallized polysilicon, and
wherein said crystallized polysilicon has been crystallized from a heat sourced from said source or drain of said channel.
14. The device according to claim 8 ,
wherein at least one of said memory transistor is self-aligned to an overlaying memory transistor.
15. A 3D memory device, the device comprising:
a plurality of memory cells,
wherein each of said plurality of memory cells comprises at least one memory transistor,
wherein each of said at least one memory transistor comprises a source, a channel and a drain; and
a plurality of bit-line pillars,
wherein each of said bit-line pillars is directly connected to a plurality of said sources or drains,
wherein said channel comprises crystallized polysilicon, and
wherein said crystallized polysilicon has been crystallized from a heat sourced from said source or drain of said channel.
16. The device according to claim 15 ,
wherein each of said bit-line pillars comprise metal atoms such that said bit-line pillars have at least partial metallic properties.
17. The device according to claim 15 ,
wherein said 3D memory comprises a NOR or an AND memory architecture.
18. The device according to claim 15 ,
wherein said plurality of memory cells comprise a metalized source or drain.
19. The device according to claim 15 ,
wherein said plurality of memory cells comprise a tunneling oxide thinner than 1 nm.
20. The device according to claim 15 ,
wherein at least one of said memory transistor is self-aligned to an overlaying memory transistor.