Analog to digital converter device and capacitor weight calibration method
An analog to digital converter device includes a capacitor array, a digital logic circuit, and a comparator circuit. The capacitor array includes first capacitors, a capacitor to be calibrated, and compensation capacitors. The digital logic circuit performs a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and converts an input signal to bits via the capacitor array after the calibration is performed. The comparator circuit compares a testing signal with a predetermined voltage to generate the decision signal. The testing signal is generated by the first capacitors and the capacitor to be calibrated in response to the calibration. The digital logic circuit further selects at least one of the compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the bits.
1. An analog to digital converter device, comprising:
a capacitor array comprising a plurality of first capacitors, a capacitor to be calibrated, and a plurality of compensation capacitors, wherein a capacitance value of each of the plurality of compensation capacitors is less than a capacitance value of each of the plurality of first capacitors;
a digital logic circuit configured to perform a calibration on the capacitor to be calibrated, in order to calibrate a weighed value of the capacitor to be calibrated according to a decision signal, and to convert an input signal to a plurality of bits via the capacitor array after the calibration is performed; and
a comparator circuit configured to compare a testing signal with a predetermined voltage to generate the decision signal, wherein the testing signal is generated by the plurality of first capacitors and the capacitor to be calibrated in response to the calibration, and the digital logic circuit is further configured to select at least one of the plurality of compensation capacitors, in order to adjust a digital code corresponding to a calibrated weighed value to be an integer expressed by the plurality of bits.
2. The analog to digital converter device of claim 1 , wherein the digital logic circuit is configured to output a plurality of first control signals according to the decision signal, in order to switch the capacitor to be calibrated from receiving a first reference voltage to receiving a second reference voltage, and to sequentially switch the plurality of first capacitors from receiving the second reference voltage to receiving the first reference voltage, in order to generate the testing signal.
3. The analog to digital converter device of claim 2 , wherein the digital logic circuit is configured to average the plurality of first control signals to determine the weighted value, and to determine whether the digital code is the integer expressed by the plurality of bits, in order to select the at least one of the plurality of compensation capacitors.
4. The analog to digital converter device of claim 3 , wherein if the weighted value is not the integer expressed by the plurality of bits, the digital logic circuit is configured to output a plurality of second control signals, in order to couple the at least one of the plurality of compensation capacitors in parallel to the capacitor to be calibrated.
5. The analog to digital converter device of claim 1 , wherein a capacitor having a smallest capacitance value in the plurality of first capacitors is a unit capacitor, and a capacitance value of each of the plurality of compensation capacitors is set to be less than or equal to 0.25 times of a capacitance value of the unit capacitor.
6. The analog to digital converter device of claim 1 , wherein if a value being less than 1 and greater than 0 in the weighed value is less than 0.5, the digital logic circuit is configured to select the at least one of the plurality of compensation capacitors, in order to adjust the value to be 0.5.
7. The analog to digital converter device of claim 1 , wherein if a value being less than 1 and greater than 0 in the weighed value is higher than 0.5, the digital logic circuit is configured to select the at least one of the plurality of compensation capacitors, in order to adjust the weighted value to a positive integer closet to the weighted value.
8. A capacitor weight calibration method, comprising:
performing a calibration on a capacitor to be calibrated in an analog to digital converter device, in order to calibrate a weighted value of the capacitor to be calibrated according to a decision signal, wherein the analog to digital converter device is configured to convert an input to a plurality of bits;
comparing a testing signal with a predetermined voltage, in order to generate the decision signal, wherein the testing signal is generated by a plurality first capacitors and the capacitor to be calibrated in the analog to digital converter device in response to the calibration; and
selecting at least one of a plurality of compensation capacitors according to the weighted value, in order to adjust a digital code corresponding to a calibrated weighted value to be an integer expressed by the plurality of bits, wherein a capacitance value of each of the plurality of compensation capacitors is less than a capacitance value of each of the plurality of first capacitors.
9. The capacitor weight calibration method of claim 8 , wherein selecting the at least one of the plurality of compensation capacitors according to the weighted value comprises:
if a value being less than 1 and greater than 0 in the weighed value is less than 0.5, selecting the at least one of the plurality of compensation capacitors, in order to adjust the value to be 0.5.
10. The capacitor weight calibration method of claim 8 , wherein selecting the at least one of the plurality of compensation capacitors according to the weighted value comprises:
if a value being less than 1 and greater than 0 in the weighed value is higher than 0.5, selecting the at least one of the plurality of compensation capacitors, in order to adjust the weighted value to a positive integer closet to the weighted value.
11. The capacitor weight calibration method of claim 8 , wherein performing the calibration on the capacitor to be calibrated comprises:
outputting a plurality of first control signals according to the decision signal, in order to switch the capacitor to be calibrated from receiving a first reference voltage to receiving a second reference voltage; and
sequentially switching the plurality of first capacitors from receiving the second reference voltage to receiving the first reference voltage, in order to generate the testing signal.
12. The capacitor weight calibration method of claim 11 , further comprising:
averaging the plurality of first control signals to determine the weighted value, and to determining whether the digital code is the integer expressed by the plurality of bits, in order to select the at least one of the plurality of compensation capacitors.
13. The capacitor weight calibration method of claim 12 , wherein if the weighted value is not the integer expressed by the plurality of bits, the at least one of the plurality of compensation capacitors is selected to be coupled in parallel to the capacitor to be calibrated.
14. The capacitor weight calibration method of claim 8 , wherein a capacitor having a smallest capacitance value in the plurality of first capacitors is a unit capacitor, and a capacitance value of each of the plurality of compensation capacitors is set to be less than or equal to 0.25 times of a capacitance value of the unit capacitor.