Three-dimensional memory devices and fabrication methods thereof

1. A method for forming a three-dimensional (3D) memory device, comprising:

forming an initial channel hole in a stack structure of a plurality of first layers and a plurality of second layers alternatingly arranged over a substrate;

forming an offset between a side surface of each one of the plurality of first layers and a side surface of each one of the plurality of second layers on a sidewall of the initial channel hole to form a channel hole;

forming a semiconductor channel by filling the channel hole with a channel-forming structure, the semiconductor channel having a memory layer comprising a plurality of first memory portions each surrounding a bottom of a respective second layer and a plurality of second memory portions each connecting adjacent first memory portions;

forming a first initial slit opening extending through the stack structure and exposing the substrate; and

removing, through the first initial slit opening, the plurality of second memory portions to retain the plurality of first memory portions, the plurality of first memory portions being disconnected from one another.

2. The method of claim 1 , wherein removing the plurality of second memory portions includes:

removing the plurality of first layers through the first initial slit to form a plurality of lateral recesses that expose portions of the semiconductor channel; and

performing an etching process on the exposed portions of the semiconductor channel through the plurality of lateral recesses and the first initial slit opening to remove the plurality of second memory portions.

3. The method of claim 2 , wherein

filling the channel hole with a channel-forming structure comprises:

forming a blocking layer over a sidewall of the channel hole,

forming the memory layer over the blocking layer,

forming a tunneling layer over the memory layer,

forming a semiconductor layer over the tunneling layer, and

forming a dielectric core over the semiconductor layer to fill up the channel hole; and

removing the plurality of second memory portions includes removing a portion of the blocking layer over each one of the plurality of the second memory portions and removing the plurality of second memory portions to expose a portion of the tunneling layer under each one of the plurality of second memory portions.

4. The method of claim 1 , wherein forming the offset comprises removing a portion of the side surface of each one of the plurality of first layers on the sidewall of the initial channel hole.

5. The method of claim 4 , wherein removing the portion of the side surface of each one of the plurality of first layers comprises performing a recess etching process that selectively etches the plurality of first layers over the plurality of second layers.

6. The method of claim 1 , wherein the plurality of first layers and the plurality of second layers are formed by:

alternatingly depositing a plurality of first material layers and a plurality of second material layers over the substrate to form an initial stack structure over the substrate, the plurality of first material layers having a different etching selectivity than the plurality of second material layers; and

repetitively etching the plurality of first material layers and the plurality of second material layers to form the stack structure having the plurality of first layers and the plurality of second layers arranged in a staircase structure.

7. The method of claim 6 , wherein depositing the plurality of first material layers comprises depositing at least one of a silicon nitride material layer, a silicon oxide material layer, or a silicon oxynitride material layer.