IP Library › Granted Patent US 11,100,999

Granted Patent B2

US 11,100,999 · App. 17/101,029 · Granted Aug 24, 2021

Semiconductor memory device

Inventors: Hiroshi Sukegawa (Tokyo, JP); Ikuo Magaki (Kawasaki, JP); Tokumasa Hara (Kawasaki, JP); Shirou Fujita (Kamakura, JP)

Assignee: Toshiba Memory Corporation

G11C16/10 G06F3/0604 G06F3/064 G06F3/0659 G06F3/0679 G11C16/0483 G11C16/08 G11C16/3418 H01L27/11582

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Quick Facts

Patent No.: US 11,100,999
App. No.: 17/101,029
Granted: Aug 24, 2021
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

A controller controls a memory including first and second strings. The first and second strings configure first and second string groups, respectively. In each string group, a set of memory cell transistors each from each string configures a unit. The controller is configured to: sequentially write, in the first string group, data in first units to which serially-coupled memory cell transistors respectively belong; sequentially write, in the second string group, data in first units to which serially-coupled memory cell transistors respectively belong; and sequentially write, in the first string group, data in second units to which serially-coupled memory cell transistors respectively belong.

Claims (91)

1. A memory system comprising:

a nonvolatile semiconductor memory device comprising:

first and second strings, each of the first and second strings including a plurality of memory cells and a select transistor, the plurality of memory cells being connected in series, the select transistor being electrically connected in series with the memory cells, the memory cells including a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell;

a bit line electrically connected to the first and the second strings;

a first select gate line electrically connected to a gate of the select transistor of the first string;

a second select gate line electrically connected to a gate of the select transistor of the second string;

a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string;

a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string,

a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; and

a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string, and

a controller configured to perform a first write process, to perform a second write process after the first write process, to perform a third write process after the second write process, and to perform a fourth write process after the third write process, wherein

the first write process includes writing data in the first memory cell of the first string and writing data in the second memory cell of the first string after the writing in the first memory cell of the first string,

the second write process includes writing data in the first memory cell of the second string and writing data in the second memory cell of the second string after the writing in the first memory cell of the second string,

the third write process includes writing data in the third memory cell of the first string and writing data in the fourth memory cell of the first string after the writing in the third memory cell of the first string, and

the fourth write process includes writing data in the third memory cell of the second string and writing data in the fourth memory cell of the second string after the writing in the third memory cell of the second string.

2. The memory system according to claim 1 , wherein:

a voltage for selection is applied to the first select gate line when the data are written in the first memory cell of the first string in the first write process,

the voltage for selection is applied to the second select gate line when the data are written in the first memory cell of the second string in the second write process,

the voltage for selection is applied to the first select gate line when the data are written in the second memory cell of the first string in the first write process,

the voltage for selection is applied to the second select gate line when the data are written in the second memory cell of the second string in the second write process,

the voltage for selection is applied to the first select gate line when the data are written in the third memory cell of the first string in the third write process,

the voltage for selection is applied to the second select gate line when the data are written in the third memory cell of the second string in the fourth write process,

the voltage for selection is applied to the first select gate line when the data are written in the fourth memory cell of the first string in the third write process, and

the voltage for selection is applied to the second select gate line when the data are written in the fourth memory cell of the second string in the fourth write process.

3. The memory system according to claim 1 , wherein:

the first memory cell of the first string is between the select transistor of the first string and the second memory cell of the first string,

the first memory cell of the first string is between the select transistor of the first string and the third memory cell of the first string,

the first memory cell of the second string is between the select transistor of the second string and the second memory cell of the second string, and

the first memory cell of the second string is between the select transistor of the second string and the third memory cell of the second string.

4. The memory system according to claim 1 , wherein:

the first to fourth word lines are located away from the bit line along a stack direction in the nonvolatile semiconductor memory device,

the first word line is closer to the bit line than the second word line,

the third word line is closer to the bit line than the fourth word line, and

the first word line is closer to the bit line than the third word line.

5. The memory system according to claim 1 , wherein:

the second word line is adjacent to the first word line,

the third word line is adjacent to the second word line, and

the fourth word line is adjacent to the third word line.

6. The memory system according to claim 1 , wherein:

the nonvolatile semiconductor memory device comprises a block as a unit of data erasing, and

the block comprises the first and second strings.

7. The memory system according to claim 1 , wherein:

each of the first to fourth memory cells is capable of storing data of two bits.

8. The memory system according to claim 1 , wherein

the memory system is connectable to a host device, and

each of the data written in the first memory cell of the first string, the data written in the second memory cell of the first string, the data written in the third memory cell of the first string, the data written in the fourth memory cell of the first string, the data written in the first memory cell of the second string, the data written in the second memory cell of the second string, the data written in the third memory cell of the second string and the data written in the fourth memory cell of the second string is based on a write command received from the host device.

9. A method of controlling a nonvolatile semiconductor memory, the nonvolatile semiconductor memory including:

a bit line electrically connected to the first and the second strings;

a first select gate line electrically connected to a gate of the select transistor of the first string;

a second select gate line electrically connected to a gate of the select transistor of the second string;

a first word line electrically connected to gates of the first memory cell of the first string and the first memory cell of the second string;

a second word line electrically connected to gates of the second memory cell of the first string and the second memory cell of the second string,

a third word line electrically connected to gates of the third memory cell of the first string and the third memory cell of the second string; and

a fourth word line electrically connected to gates of the fourth memory cell of the first string and the fourth memory cell of the second string, the method comprising:

performing a first write process;

performing a second write process after performing the first write process;

performing a third write process after performing the second write process; and

performing a fourth write process after performing the third write process, wherein

10. The method according to claim 9 , further comprising:

applying a voltage for selection to the first select gate line when the data are written in the first memory cell of the first string in the first write process,

applying the voltage for selection to the second select gate line when the data are written in the first memory cell of the second string in the second write process,

applying the voltage for selection to the first select gate line when the data are written in the second memory cell of the first string in the first write process,

applying the voltage for selection to the second select gate line when the data are written in the second memory cell of the second string in the second write process,

applying the voltage for selection to the first select gate line when the data are written in the third memory cell of the first string in the third write process,

applying the voltage for selection to the second select gate line when the data are written in the third memory cell of the second string in the fourth write process,

applying the voltage for selection to the first select gate line when the data are written in the fourth memory cell of the first string in the third write process, and

applying the voltage for selection to the second select gate line when the data are written in the fourth memory cell of the second string in the fourth write process.

11. The method according to claim 9 , wherein:

the first memory cell of the first string is between the select transistor of the first string and the second memory cell of the first string,

the first memory cell of the first string is between the select transistor of the first string and the third memory cell of the first string,

the first memory cell of the second string is between the select transistor of the second string and the second memory cell of the second string, and

the first memory cell of the second string is between the select transistor of the second string and the third memory cell of the second string.

12. The method according to claim 9 , wherein:

the first to fourth word lines are located away from the bit line along a stack direction in the nonvolatile semiconductor memory,

the first word line is closer to the bit line than the second word line,

the third word line is closer to the bit line than the fourth word line, and

the first word line is closer to the bit line than the third word line.

13. The method according to claim 9 , wherein:

the second word line is adjacent to the first word line,

the third word line is adjacent to the second word line, and

the fourth word line is adjacent to the third word line.

14. The method according to claim 9 , wherein:

the nonvolatile semiconductor memory comprises a block as a unit of data erasing, and

the block comprises the first and second strings.

15. The method according to claim 9 , wherein:

each of the first to fourth memory cells is capable of storing data of two bits.

Assignments (3)

CHANGE OF NAME AND ADDRESS Recorded Feb 4, 2022

From: K.K PANGEA

To: TOSHIBA MEMORY CORPORATION

Reel/Frame 058957/0124 →

CHANGE OF NAME AND ADDRESS Recorded Jan 31, 2022

From: TOSHIBA MEMORY CORPORATION

To: KIOXIA CORPORATION

Reel/Frame 058905/0582 →

MERGER Recorded Jan 31, 2022

From: TOSHIBA MEMORY CORPORATION

To: K.K PANGEA

Reel/Frame 058946/0675 →

Continuity (6)

Continuation 16656673 · Oct 18, 2019

Continuation 16045956 · Jul 26, 2018

Continuation 15230857 · Aug 8, 2016

Continuation 14200641 · Mar 7, 2014

Provisional Application 61861456 · Aug 2, 2013

Related Publication 20210074363A1 · Mar 11, 2021