Inverse lithography and machine learning for mask synthesis
Techniques relating to synthesizing masks for use in manufacturing a semiconductor device are disclosed. A plurality of training masks, for a machine learning (ML) model, are generated by synthesizing one or more polygons, relating to a design pattern for the semiconductor device, using Inverse Lithography Technology (ILT) ( 106 ). The ML model is trained using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs ( 108 ). The trained ML model is configured to synthesize one or more masks, for use in manufacturing the semiconductor device, based on the design pattern ( 110 ).
1. A method comprising:
generating a plurality of training masks for a machine learning (ML) model by synthesizing one or more polygons from a design pattern for a semiconductor device, using Inverse Lithography Technology (ILT); and
training the ML model using both the plurality of training masks generated using ILT, and the design pattern for the semiconductor device, as inputs, wherein the trained ML model is configured to synthesize one or more masks for use in manufacturing the semiconductor device based on the design pattern, wherein prior to training the ML model, one or more training masks, of the plurality of training masks, are pre-processed to improve symmetry of the one or more training masks.
2. The method of claim 1 , wherein the ML model is trained using rasterized transformations of the plurality of training masks.
3. The method of claim 1 , wherein the ML model comprises a plurality of dilated convolutions.
4. The method of claim 3 , wherein the ML model receives as input a rasterized transformation relating to the design pattern.
5. The method of claim 4 , wherein the ML model further receives as input a rasterized transformation relating to a correction of the design pattern.
6. The method of claim 4 , wherein the ML model further receives as input a simulated image relating to using the design pattern as a mask for manufacturing the semiconductor device.
7. The method of claim 3 , wherein the ML model further comprises at least one mirrored or rotated convolution.
8. A system comprising:
a processor; and
a memory storing instructions, which when executed by the processor, cause the processor to perform operations comprising:
receiving a trained machine learning (ML) model, wherein the ML model is trained using a plurality of training masks generated by synthesizing one or more polygons from a design pattern for a semiconductor device, using Inverse Lithography Technology (ILT), and wherein prior to training the ML model, one or more training masks, of the plurality of training masks, are pre-processed to improve symmetry of the one or more training masks;
generating one or more masks for use in manufacturing the semiconductor device by providing the design pattern for the semiconductor device to the trained ML model; and
converting the generated one or more masks from at least one of a rasterized representation or a level-set representation to a polygon representation for use in manufacturing the semiconductor device.
9. The system of claim 8 , wherein the ML model is further trained using the design pattern for the semiconductor device.
10. The system of claim 8 , wherein the ML model is trained using rasterized transformations of the plurality of training masks.
11. The system of claim 8 , wherein the operation comprises converting the generated one or more masks from the rasterized representation to the polygon representation.
12. The system of claim 11 , wherein converting the generated one or more masks from the rasterized representation to the polygon representation comprises contouring the rasterized representation to generate a plurality of angle polygons.
13. The system of claim 8 , wherein the operation comprises converting the generated one or more masks from a level-set representation to the polygon representation.