IP Library Granted Patent US 12,446,333
Granted Patent B2
US 12,446,333 · App. 17/102,623 · Granted Oct 14, 2025

Surface uniformity control in pixel structures of image sensors

Inventors: Po-Chun Liu (Hsinchu, TW); Eugene I-Chun Chen (Taipei, TW); Chun-Kai Lan (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10F39/011H10F39/199
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Quick Facts
Patent No.
US 12,446,333
App. No.
17/102,623
Granted
Oct 14, 2025
Kind
B2
Abstract

A semiconductor device with an image sensor and a method of fabricating the same are disclosed. The method includes depositing a dielectric layer on a substrate, forming a trench within the dielectric layer and the substrate, forming an epitaxial structure within the trench, and forming a barrier layer with first and second layer portions. The first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure. The method further includes forming a capping layer on the epitaxial structure and adjacent to the barrier layer, selectively doping regions of the epitaxial structure and the capping layer, selectively forming a silicide layer on the doped regions, depositing an etch stop layer on the silicide layer, and forming conductive plugs on the silicide layer through the etch stop layer.

Claims (51)

1. A method, comprising:

forming a dielectric layer on a substrate;

forming a trench in the dielectric layer and the substrate;

forming an epitaxial structure in the trench;

forming a barrier layer with first and second layer portions, wherein the first layer portion is formed on a sidewall portion of the trench that is not covered by the epitaxial structure;

forming a capping layer on the epitaxial structure and adjacent to the barrier layer;

selectively doping regions of the epitaxial structure and the capping layer;

forming a silicide layer on the doped regions;

forming an etch stop layer on the silicide layer; and

forming conductive plugs on the silicide layer through the etch stop layer.

2. The method of claim 1 , wherein forming the epitaxial structure comprises:

growing the epitaxial structure within the trench; and

etching the epitaxial structure, wherein the sidewall portion of the trench is exposed after the etching.

3. The method of claim 1 , wherein forming the epitaxial structure comprises:

polishing the epitaxial structure;

etching the epitaxial structure; and

cleaning the epitaxial structure after the etching, wherein a surface portion of the substrate is exposed after the cleaning and wherein the second layer portion is formed on the surface portion.

4. The method of claim 1 , wherein the second layer portion is formed on a front side surface portion of the substrate that is adjacent to the sidewall portion of the trench, and

wherein forming the barrier layer comprises oxidizing the sidewall portion of the trench and the front side surface portion of the substrate.

5. The method of claim 1 , wherein forming the barrier layer comprises performing an oxidation process with an ozone-based oxidizing solution.

6. The method of claim 1 , wherein forming the barrier layer comprises performing an oxidation process with a hydrogen peroxide-based solution.

7. The method of claim 1 , wherein forming the capping layer comprises epitaxially growing the capping layer on the epitaxial structure.

8. The method of claim 1 , further comprising:

forming an oxide layer on the epitaxial structure during forming the barrier layer; and

performing an anneal process to remove the oxide layer.

9. A method, comprising:

depositing a first dielectric layer on a substrate;

epitaxially growing a first semiconductor layer in the substrate;

forming a second dielectric layer on a substrate region of the substrate, wherein the substrate region is between the first dielectric layer and the first semiconductor layer;

epitaxially growing a second semiconductor layer on the first semiconductor layer;

doping the first and second semiconductor layers to form a first doped region;

doping the first and second semiconductor layers to form a second doped region; and

forming contact structures on the first and second doped regions.

10. The method of claim 9 , further comprising forming a trench in the first dielectric layer and the substrate to epitaxially grow the first semiconductor layer in the trench.

11. The method of claim 9 , further comprising etching the first semiconductor layer to expose a sidewall of the substrate.

12. The method of claim 9 , further comprising performing a cleaning process on the first semiconductor layer, wherein the cleaning process exposes a surface portion of the substrate.

13. The method of claim 9 , wherein forming the second dielectric layer comprises performing an oxidation process with an ozone-based oxidizing solution.

14. The method of claim 9 , wherein forming the second dielectric layer comprises performing an oxidation process with a hydrogen peroxide-based solution.

15. The method of claim 9 , further comprising performing an annealing process on the second dielectric layer prior to epitaxially growing the second semiconductor layer.

16. The method of claim 9 , wherein epitaxially growing the second semiconductor layer comprises epitaxially growing a semiconductor material different from a semiconductor material of the first semiconductor layer.

17. A method, comprising:

forming a pixel structure, comprising:

forming a trench in a substrate,

forming an epitaxial structure in a bottom portion of the trench,

forming an oxide layer along top edges of the substrate exposed in a top portion of the trench, and

forming a capping layer on the epitaxial structure and adjacent to the oxide layer;

forming an isolation structure adjacent to the pixel structure; and

forming a contact pad structure adjacent to the isolation structure.

18. The method of claim 17 , wherein forming the oxide layer comprises performing an oxidation process on surfaces of the trench uncovered by the epitaxial structure.

19. The method of claim 17 , wherein forming the isolation structure comprises forming doped regions in the substrate adjacent to the pixel structure.

20. The method of claim 17 , wherein forming the pixel structure further comprises forming doped regions in the epitaxial structure and the capping layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 24, 2020
From: LIU, PO-CHUN; CHEN, EUGENE I-CHUN; LAN, CHUN-KAI
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054462/0448 →
Continuity (2)
Provisional Application 63031752 · May 29, 2020
Related Publication 20210375669A1 · Dec 2, 2021
References Cited (20)
US 5756396A · Lee et al. · 1998 [cited by applicant]
US 9799689B2 · Cheng · 2017 [cited by examiner]
US 9871132B1 · Liu et al. · 2018 [cited by applicant]
US 10861896B2 · Liu et al. · 2020 [cited by applicant]
US 11031425B2 · Seo et al. · 2021 [cited by applicant]
US 20090101909A1 · Chen et al. · 2009 [cited by applicant]
US 20110084308A1 · Loh · 2011 [cited by examiner]
US 20150228793A1 · Chen et al. · 2015 [cited by applicant]
US 20160071799A1 · Hsieh et al. · 2016 [cited by applicant]
US 20170092679A1 · Wan et al. · 2017 [cited by applicant]
US 20180158850A1 · Wu et al. · 2018 [cited by applicant]
US 20190081099A1 · Tamaki et al. · 2019 [cited by applicant]
US 20190088700A1 · Yang · 2019 [cited by applicant]
US 20190132536A1 · Watanabe et al. · 2019 [cited by applicant]
CN 104835780A · 2015 [cited by applicant]
CN 105448863A · 2016 [cited by applicant]
CN 108886045A · 2018 [cited by applicant]
JP 2013020998A · 2013 [cited by applicant]
KR 20070056691A · 2007 [cited by applicant]
KR 20200012816A · 2020 [cited by applicant]