IP Library Granted Patent US 10,062,721
Granted Patent B2
US 10,062,721 · App. 15/378,906 · Granted Aug 28, 2018

Elevated photodiode with a stacked scheme

Inventors: Meng-Hsun Wan (Taipei, TW); Yi-Shin Chu (Hsin-Chu, TW); Szu-Ying Chen (Toufen Township, TW); Pao-Tung Chen (Tainan Hsien, TW); Jen-Cheng Liu (Hsin-Chu, TW); Dun-Nian Yaung (Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L27/14632H01L27/1463H01L27/1464H01L27/1469H01L27/14621H01L27/14627H01L27/14634H01L27/14636H01L27/14645H01L27/14685H01L27/14687H01L27/14689H01L31/022466H01L31/03762H01L31/035218H01L31/18H04N5/378
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Quick Facts
Patent No.
US 10,062,721
App. No.
15/378,906
Granted
Aug 28, 2018
Kind
B2
Abstract

A device includes an image sensor chip having formed therein an elevated photodiode, and a device chip underlying and bonded to the image sensor chip. The device chip has a read out circuit electrically connected to the elevated photodiode.

Claims (36)

1. A method of manufacturing a device, the method comprising:

forming a recess within a semiconductor substrate;

depositing a first electrode within the recess;

depositing a photoelectrical conversion layer within the recess; and

depositing a second electrode over the photoelectrical conversion layer, the second electrode being transparent and extending out of the recess.

2. The method of claim 1 , wherein the forming the recess forms the recess with dielectric sidewalls.

3. The method of claim 2 , wherein the dielectric sidewalls surround the recess.

4. The method of claim 1 , further comprising bonding the semiconductor substrate to a semiconductor wafer.

5. The method of claim 4 , wherein the semiconductor wafer comprises a read out circuit.

6. The method of claim 1 , further comprising forming a through via extending from a first side of the semiconductor substrate to a second side of the semiconductor substrate opposite the first side.

7. A method of manufacturing a device, the method comprising:

manufacturing an elevated photodiode adjacent to a first side of a first semiconductor substrate, wherein the manufacturing the elevated photodiode comprises forming a recess within the first semiconductor substrate;

manufacturing a metallization layer adjacent to a second side of the first semiconductor substrate;

manufacturing first external connections in electrical connection with the metallization layer; and

bonding the first external connections with second external connections, the second external connections being in electrical connection with a second semiconductor substrate.

8. The method of claim 7 , wherein the manufacturing the elevated photodiode further comprises:

depositing a first electrode within the recess;

depositing a photoelectric conversion layer within the recess and over the first electrode; and

depositing a second electrode in electrical connection with the photoelectric conversion layer.

9. The method of claim 8 , wherein the depositing the second electrode deposits the second electrode outside of the recess.

10. The method of claim 8 , wherein the forming the recess comprises at least in part a etching process.

11. The method of claim 7 , further comprising sawing the second semiconductor substrate after the bonding the first external connections with the second external connections.

12. The method of claim 7 , wherein the second semiconductor substrate comprises a read out circuit.

13. The method of claim 12 , wherein the read out circuit further comprises a correlated double sampling circuit.

14. A method of manufacturing a semiconductor device, the method comprising:

providing a first semiconductor die;

providing a second semiconductor die;

bonding the first semiconductor die to the second semiconductor die such that a pixel unit extends between the first semiconductor die and the second semiconductor die, the pixel unit comprising:

an elevated photodiode; and

read out circuitry.

15. The method of claim 14 , wherein the pixel unit comprises a transfer transistor located on the first semiconductor die and wherein the elevated photodiode is located on the first semiconductor die.

16. The method of claim 14 , further comprising a deep trench isolation structure located within the first semiconductor die, wherein the deep trench isolation structure comprises a plurality of rings, at least one of the plurality of rings encircling the pixel unit.

17. The method of claim 14 , wherein the bonding the first semiconductor die to the second semiconductor die further comprises bonding a first wafer to a second wafer.

18. The method of claim 14 , wherein the read out circuitry comprises an image signal processing circuit.

19. The method of claim 14 , wherein the pixel unit further comprises a dielectric material, the dielectric material having a first surface level with a surface of a photoelectrical conversion layer and a second surface level with a first electrode, wherein the photoelectrical conversion layer and the first electrode are portions of the elevated photodiode.

20. The method of claim 19 , wherein the elevated photodiode further comprises a second electrode, the second electrode in physical contact with a surface of the dielectric material.

Continuity (5)
Continuation 14841252 · Aug 31, 2015
Continuation 14531820 · Nov 3, 2014
Division 13671330 · Nov 7, 2012
Provisional Application 61677851 · Jul 31, 2012
Related Publication 20170092679A1 · Mar 30, 2017