Systems and methods for preservation of qubits
Embodiments of quantum ring oscillator-based coherence preservation circuits including a cascaded set of stages are described. Embodiments of such quantum ring oscillator-based coherence preservation circuits allow the internal (superpositioned) quantum state information of stored qubits to be preserved over long periods of time and present options for the measurement and potential correction of both deterministic and non-deterministic errors without disturbing the quantum information stored in the structure itself.
1. A system for the quantum coherence preservation of a qubit, comprising:
an oscillator adapted to operate in a quantum mode and in a classical mode, the oscillator including a plurality of cascaded stages, each stage including:
a circuit adapted to perform a corresponding operation in either the classical mode or in the quantum mode,
an input, and
an output, wherein the stage is adapted to evolve a qubit between a first state on the input and a second state on the output,
wherein the stages are cascaded such that the input of one stage is coupled to the output of a previous stage and the input of a first stage of the cascaded stages is coupled to the output of a last stage of the cascaded stages to form a feedback circuit path, and
wherein the classical mode is adapted for performing a quantum operation simultaneously on a plurality of independent qubits.
2. The system of claim 1 , wherein the circuit for each stage is a square root of NOT gate.
3. The system of claim 1 , wherein the circuit for each state is a Hadamard gate.
4. The system of claim 1 , wherein the oscillator includes a Bell State oscillator (BSO), including:
a first stage comprising a first Bell State generator, including a first Hadamard gate and a first CNOT gate, the first Hadamard gate having an input and an output and the first CNOT gate having an input and an output;
a second stage comprising a second Bell State generator, including a second Hadamard gate and a second CNOT gate, the second Hadamard gate having an input and an output and the second CNOT gate having an input and an output, wherein the input of the second Hadamard gate is coupled to the output of the first Hadamard gate of the first Bell State generator and the input of the second CNOT gate is coupled to the output of the first CNOT gate of the first Bell State generator;
a third stage comprising a third Bell State generator, including a third Hadamard gate and a third CNOT gate, the third Hadamard gate having an input and an output and the third CNOT gate having an input and an output, wherein the input of the third Hadamard gate is coupled to the output of the second Hadamard gate of the second Bell State generator and the input of the third CNOT gate is coupled to the output of the second CNOT gate of the second Bell State generator; and
a fourth stage comprising a fourth Bell State generator, including a fourth Hadamard gate and a fourth CNOT gate, the fourth Hadamard gate having an input and an output and the fourth CNOT gate having an input and an output, wherein the input of the fourth Hadamard gate is coupled to the output of the third Hadamard gate of the third Bell State generator and the input of the fourth CNOT gate is coupled to the output of the third CNOT gate of the third Bell State generator, and wherein the feedback circuit path is formed from the coupling of the input of the first Hadamard gate of the first Bell State generator to the output of the fourth Hadamard gate of the fourth Bell State generator and the coupling of the input of the first CNOT gate of the first Bell State generator to the output of the fourth CNOT gate of the fourth Bell State generator.
5. The system of claim 1 , wherein the oscillator includes a Greenberger, Horne and Zeilinger (GHZ) state oscillator (GSO), including:
a first stage comprising a first GHZ state generator, including a first Hadamard gate, a first CNOT gate and a second CNOT gate, the first Hadamard gate having an input and an output, the first CNOT gate having an input and an output and the second CNOT gate having an input and an output;
a second stage comprising a second GHZ state generator, including a second Hadamard gate, a third CNOT gate and a fourth CNOT gate, the second Hadamard gate having an input and an output, the third CNOT gate having an input and an output, and the fourth CNOT gate having an input and an output, wherein the input of the second Hadamard gate is coupled to the output of the first Hadamard gate of the first GHZ state generator, the input of the third CNOT gate is coupled to the output of the second CNOT gate of the first GHZ state generator and the input of the fourth CNOT gate is coupled to the output of the second CNOT gate of the first GHZ state generator;
a third stage comprising a third GHZ state generator, including a third Hadamard gate, a fifth CNOT gate and a sixth CNOT gate, the third Hadamard gate having an input and an output, the fifth CNOT gate having an input and an output and the sixth CNOT gate having an input and an output, wherein the input of the third Hadamard gate is coupled to the output of the second Hadamard gate of the second GHZ state generator, the input of the fifth CNOT gate is coupled to the output of the third CNOT gate of the second GHZ state generator and the input of the sixth CNOT gate is coupled to the output of the fourth CNOT gate of the second GHZ state generator; and
a fourth stage comprising a fourth GHZ state generator, including a fourth Hadamard gate, a seventh CNOT gate, and a eighth CNOT gate, the fourth Hadamard gate having an input and an output, the seventh CNOT gate having an input and an output, and the eighth CNOT gate having an input and an output, wherein the input of the fourth Hadamard gate is coupled to the output of the third Hadamard gate of the third GHZ state generator, the input of the seventh CNOT gate is coupled to the output of the fifth CNOT gate of the third GHZ state generator, and the input of the eighth CNOT gate is coupled to the output of the sixth CNOT gate of the third GHZ state generator, and wherein the feedback circuit path is formed from the coupling of the input of the first Hadamard gate of the first GHZ state generator to the output of the fourth Hadamard gate of the fourth GHZ state generator, the coupling of the input of the first CNOT gate of the first GHZ state generator to the output of the seventh CNOT gate of the fourth GHZ state generator, and the coupling of the input of the second CNOT gate of the first Bell State generator to the output of the eighth CNOT gate of the fourth GHZ state generator.
6. The system of claim 1 , further comprising error correction circuitry adapted to apply error correction to the oscillator.
7. The system of claim 6 , wherein the error correction circuitry is coupled to the quantum oscillator in the feedback circuit path of the quantum oscillator.
8. The system of claim 6 , wherein the error correction circuitry applies error correction based on an error detection qubit.
9. The system of claim 8 , wherein the error detection qubit is a basis-state carrier.
10. The system of claim 6 , wherein the error correction is non-deterministic error correction.
11. A system for the quantum coherence preservation of a qubit, comprising:
a first oscillator comprising a first plurality of cascaded stages such that the input of one stage of the first plurality is coupled to the output of a previous stage of the first plurality and the first plurality of cascaded stages comprises a feedback circuit path, wherein each stage of the first plurality of cascaded stages is a quantum basis state stage or an intermediate quantum state stage and the first plurality of stages are cascaded such the stages of the first plurality of cascaded stages alternate between the quantum basis state stage and the intermediate quantum basis state stage; and
a second oscillator comprising a second plurality of cascaded stages such that the input of one stage of the second plurality is coupled to the output of a previous stage of the second plurality and the second plurality of cascaded stages comprises a feedback circuit path, wherein each stage of the second plurality of cascaded stages is the quantum basis state stage or the intermediate quantum state stage and the second plurality of stages are cascaded such the stages of the second plurality of cascaded stages alternate between the quantum basis state stage and the intermediate quantum basis state stage,
wherein the first oscillator is coupled to the second oscillator, the coupling of the first oscillator to the second oscillator comprising a coupling of a first stage of the first plurality of cascades stages of the first oscillator to a second stage of the second plurality of cascade stage of the second oscillator, wherein the first stage of the first plurality of cascaded stages of the first oscillator is the intermediate quantum basis state stage and the second stage of the second plurality of cascade stage of the second oscillator is the quantum basis state stage or the intermediate quantum state stage.
12. The system of claim 11 , wherein each of the first plurality of stages includes a square root of NOT gate or a Hadamard gate.
13. The system of claim 12 , wherein each of the second plurality of stages includes a square root of NOT gate or a Hadamard gate.
14. The system of claim 11 , wherein the first oscillator or second oscillator comprises a Bell State oscillator (BSO).
15. The system of claim 11 , wherein the first oscillator or second oscillator comprises a Greenberger, Horne and Zeilinger (GHZ) state oscillator (GSO).
16. The system of claim 11 , wherein the first oscillator or second oscillator further comprising error correction circuitry adapted to apply error correction to the oscillator.
17. The system of claim 16 , wherein the error correction circuitry applies error correction based on an error detection qubit.
18. The system of claim 17 , wherein the error detection qubit is a basis-state carrier.
19. The system of claim 16 , wherein the error correction is non-deterministic error correction.
20. The system of claim 11 , wherein the error correction circuitry is coupled to the first oscillator or the second oscillator in the feedback circuit path of the first oscillator or the second oscillator.