Gap spacer for backside contact structure

1. A semiconductor device, comprising:

a source feature disposed over a backside source contact;

a drain feature disposed over a backside dielectric layer;

a plurality of channel members each extending between the source feature and the drain feature; and

a gate structure wrapping around each of the plurality of channel members, the gate structure being disposed over the backside dielectric layer,

wherein the backside source contact is spaced apart from the backside dielectric layer by a gap.

2. The semiconductor device of claim 1 , further comprising:

a first liner and a second liner disposed between the backside dielectric layer and the drain feature,

wherein the first liner is in contact with the drain feature and the second liner is spaced apart from the drain feature by the first liner.

3. The semiconductor device of claim 2 , wherein the first liner and the second liner extend between the gate structure and the backside dielectric layer.

4. The semiconductor device of claim 2 , wherein the first liner and the second liner comprise silicon oxide, hafnium silicide, silicon oxycarbide, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yittrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, or silicon carbonitride.

5. The semiconductor device of claim 2 ,

wherein the first liner comprises a first vertical portion that extends along a sidewall of the backside source contact,

wherein the second liner comprises a second vertical portion that extends along a sidewall of the backside dielectric layer.

6. The semiconductor device of claim 5 , further comprising a third liner disposed between the first vertical portion of the first liner and the backside source contact.

7. The semiconductor device of claim 5 , wherein the gap is disposed between the first vertical portion of the first liner and the second vertical portion of the second liner.

8. The semiconductor device of claim 7 , further comprising:

a seal plug disposed between the first vertical portion and the second vertical portion,

wherein the gap is disposed in a space defined by the first vertical portion, the second vertical portion, and the seal plug.

9. A semiconductor structure, comprising:

a backside source contact;

a source feature disposed over the backside source contact;

a contact etch stop layer disposed over the source feature;

a first liner extending along sidewalls of the backside source contact;

a second liner extending along the first liner; and

a gap disposed between the first liner and the second liner.

10. The semiconductor structure of claim 9 , further comprising:

a drain feature;

a plurality of channel members each extending between the source feature and the drain feature; and

a gate structure wrapping around each of the plurality of channel members,

wherein the drain feature and the gate structure are disposed over a backside dielectric layer.

11. The semiconductor structure of claim 10 , wherein a portion of the first liner and a portion of the second liner extend between the gate structure and the backside dielectric layer as well as between the drain feature and the backside dielectric layer.

12. The semiconductor structure of claim 10 , wherein the backside source contact is spaced apart from the backside dielectric layer by the first liner, the second liner, and the gap.

13. The semiconductor structure of claim 10 , wherein the gap extends below the gate structure.

14. The semiconductor structure of claim 10 , wherein the gap extends below the drain feature.

15. The semiconductor structure of claim 9 , further comprising:

a third liner disposed between the first liner and the backside source contact,

wherein the third liner comprises silicon oxide, hafnium silicide, silicon oxycarbide, aluminum oxide, zirconium silicide, aluminum oxynitride, zirconium oxide, hafnium oxide, titanium oxide, zirconium aluminum oxide, zinc oxide, tantalum oxide, lanthanum oxide, yttrium oxide, tantalum carbonitride, silicon nitride, silicon oxycarbonitride, silicon, zirconium nitride, silicon carbonitride, or a combination thereof.

16. A method, comprising:

receiving a workpiece comprising:

a plurality of channel members disposed over a substrate,

a gate structure wrapping around each of the plurality of channel members, and

a source feature disposed over a semiconductor plug extending into the substrate, the source feature being coupled to the plurality of channel members;

selectively removing the substrate without substantially damaging the semiconductor plug;

after the selectively removing, depositing a first liner over the semiconductor plug;

depositing a sacrificial liner over the first liner;

depositing a second liner over the sacrificial liner;

depositing a backside dielectric layer over the second liner;

performing a planarization process to expose the sacrificial liner; and

after the planarization process, selectively removing the exposed sacrificial liner to form a gap between the first liner and the second liner.

17. The method of claim 16 ,

wherein a composition of the first liner is different from a composition of the sacrificial liner,

wherein a composition of the second liner is different from the composition of the sacrificial liner.

18. The method of claim 16 , wherein the sacrificial liner comprises silicon.

19. The method of claim 16 , further comprising:

after the depositing of the sacrificial liner and before the depositing of the second liner, etching back the sacrificial liner.

20. The method of claim 16 , further comprising:

after the selectively removing of the exposed sacrificial liner, depositing a seal material over the gap; and

planarizing the seal material to form a seal plug over the gap.