Semiconductor device having nanosheet transistor and methods of fabrication thereof

1. A semiconductor device structure, comprising:

one or more first semiconductor layers, each first semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer and a fourth intermixed layer, wherein the first intermixed layer is disposed between the first semiconductor layer and the fourth intermixed layer, and the first intermixed layer comprises a first material and a second material, and the fourth intermixed layer comprises a third material and a fourth material; and

one or more second semiconductor layers disposed below and aligned with the one or more first semiconductor layers, each second semiconductor layer of the one or more second semiconductor layers is surrounded by a second intermixed layer and a third intermixed layer, wherein the second intermixed layer is disposed between the second semiconductor layer and the third intermixed layer, and the second intermixed layer comprises the first material and a fifth material, and the third intermixed layer comprises the third material and a sixth material,

wherein the second material and the fourth material are a dipole material having a first polarity, and the fifth material and the sixth material are a dipole material having a second polarity opposite of the first polarity.

2. The semiconductor device structure of claim 1 , further comprising:

a first gate electrode layer in contact with the third intermixed layer and the fourth intermixed layer.

3. The semiconductor device structure of claim 2 , further comprising:

a fifth intermixed layer in contact with the first gate electrode layer, wherein the fifth intermixed layer comprises a same material as the third intermixed layer; and

a sixth intermixed layer in contact with the first gate electrode layer, wherein the sixth intermixed layer comprises a same material as the fourth intermixed layer.

4. The semiconductor device structure of claim 3 , further comprising:

a first liner in contact with the fifth intermixed layer and the sixth intermixed layer, wherein the first liner comprises a low-k dielectric material.

5. The semiconductor device structure of claim 4 , further comprising:

an insulating material in contact with the fifth intermixed layer; and

a second liner in contact with the fifth intermixed layer, wherein the second liner is different from the first liner, and the second liner comprises a semiconductor material.

6. The semiconductor device structure of claim 4 , further comprising:

a bottom intermixed layer in contact with the fifth intermixed layer, wherein the bottom intermixed layer comprises a same material as the second intermixed layer.

7. The semiconductor device structure of claim 1 , further comprising:

a first gate electrode layer in contact with the third intermixed layer; and

a second gate electrode layer in contact with the fourth intermixed layer, wherein the second gate electrode layer is different from the first gate electrode layer.

8. The semiconductor device structure of claim 7 , further comprising:

a fifth intermixed layer in contact with the first gate electrode layer; and

a sixth intermixed layer in contact with the second gate electrode layer.

9. The semiconductor device structure of claim 1 , wherein the first material comprises an oxygen-containing material or a silicon-containing material, and the third material comprises a high-k (HK) dielectric material.

10. A semiconductor device structure, comprising:

one or more first semiconductor layers, wherein each semiconductor layer of the one or more first semiconductor layers is surrounded by a first intermixed layer, and the first intermixed layer comprises a first dipole material having a first polarity;

one or more second semiconductor layers disposed below and aligned with the one or more first semiconductor layers, wherein each semiconductor layer of the one or more second semiconductor layers is surrounded by a second intermixed layer, and the second intermixed layer comprises a second dipole material having a second polarity opposite of the first polarity;

a high-K dielectric layer in contact with the first intermixed layer and the second intermixed layer, respectively;

a first source/drain feature in contact with the one or more first semiconductor layers; and

a second source/drain feature in contact with the one or more second semiconductor layers.

11. The semiconductor device structure of claim 10 , further comprising:

a first dipole layer surrounding each semiconductor layer of the one or more first semiconductor layers, wherein the first dipole layer comprising the first dipole material, and the first intermixed layer is disposed between the first dipole layer and the high-K dielectric layer.

12. The semiconductor device structure of claim 11 , further comprising:

a second dipole layer surrounding each semiconductor layer of the one or more second semiconductor layers, wherein the second dipole layer comprising the second dipole material, and the second intermixed layer is disposed between the second dipole layer and the high-K dielectric layer.

13. The semiconductor device structure of claim 12 , further comprising:

a third intermixed layer surrounding and in contact with each semiconductor layer of the one or more first semiconductor layers, wherein the third intermixed layer comprises a third dipole material having the first polarity.

14. The semiconductor device structure of claim 13 , further comprising:

a fourth intermixed layer surrounding and in contact with each semiconductor layer of the one or more second semiconductor layers, wherein the fourth intermixed layer comprises a fourth dipole material having the second polarity opposite of the first polarity.

15. The semiconductor device structure of claim 10 , further comprising:

an interfacial layer surrounding and in contact with each semiconductor layer of the one or more first semiconductor layers and each semiconductor layer of the one or more second semiconductor layers; and

a fifth intermixed layer surrounding each semiconductor layer of the one or more first semiconductor layers, wherein the interfacial layer is disposed between the fifth intermixed layer and each semiconductor layer of the one or more first semiconductor layers, and wherein the fifth intermixed layer comprises a third dipole material having the first polarity.

16. The semiconductor device structure of claim 15 , further comprising:

a sixth intermixed layer surrounding each semiconductor layer of the one or more second semiconductor layers, wherein the interfacial layer is disposed between the sixth intermixed layer and each semiconductor layer of the one or more second semiconductor layers, and wherein the sixth intermixed layer comprises a fourth dipole material having the second polarity opposite of the first polarity.

17. The semiconductor device of claim 10 , further comprising:

a first gate electrode layer in contact with the first intermixed layer; and

a second gate electrode layer in contact with the second intermixed layer, wherein the second gate electrode layer is different from the first gate electrode layer.

18. The semiconductor device of claim 10 , wherein the one or more of first semiconductor layers have a first height, and a distance between a bottommost first semiconductor layer and a topmost second semiconductor layer has a second height greater than the first height.

19. A method for forming a semiconductor device structure, comprising:

forming a stack of layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers alternatingly stacked;

forming a first source/drain feature and a second source/drain feature, wherein the first source/drain feature is disposed below and aligned with the second source/drain feature, and the first source/drain feature and the second source/drain feature are in contact with the plurality of first semiconductor layers;

removing portions of the plurality of second semiconductor layers to expose portions of each of the plurality of first semiconductor layers;

forming an interfacial layer to surround exposed portions of each of the plurality of first semiconductor layers;

forming a first dipole layer on the interfacial layer formed on a first group of the plurality of first semiconductor layers, wherein the first dipole layer comprises a first dipole material having a first polarity;

forming a second dipole layer on the interfacial layer formed on a second group of the plurality of first semiconductor layers, wherein the second dipole layer comprises a second dipole material having a second polarity opposite of the first polarity;

subjecting the first and second dipole layers to a first thermal treatment; and

forming a high-K dielectric layer to surround the interfacial layer.

20. The method of claim 19 , further comprising:

forming a third dipole layer on the high-K dielectric layer surrounding the first group of the plurality of first semiconductor layers, wherein the third dipole layer comprises a third dipole material having the first polarity;

forming a fourth dipole layer on the high-K dielectric layer surrounding the second group of the plurality of first semiconductor layers, wherein the fourth dipole layer comprises a fourth dipole material having the second polarity opposite of the first polarity;

subjecting the third and fourth dipole layers to a second thermal treatment; and

forming a gate electrode layer to surround the high-K dielectric layer surrounding each of the plurality of first semiconductor layers.