Data latch circuit and semiconductor memory device
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
1. A data latch circuit, comprising:
a first n-channel transistor; and
a first p-channel transistor,
a gate of the first n-channel transistor and a gate of the first p-channel transistor being a common gate,
wherein the gate has a crank-like configuration in a plan view.
2. The circuit according to claim 1 , wherein
the first n-channel transistor is a driver, and
the first p-channel transistor is a load.
3. The circuit according to claim 1 , further comprising:
a second n-channel transistor;
a third n-channel transistor;
a fourth n-channel transistor; and
a second p-channel transistor,
a gate of the second n-channel transistor and a gate of the second p-channel transistor being a common gate,
one of a source or a drain of the third n-channel transistor being connected to the gate of the second n-channel transistor, the gate of the second p-channel transistor, one of a source or a drain of the first n-channel transistor, and one of a source or a drain of the first p-channel transistor,
the other of the source or the drain of the third n-channel transistor being connected to a sense amplifier,
one of a source or a drain of the fourth n-channel transistor being connected to the gate of the first n-channel transistor, the gate of the first p-channel transistor, one of a source or a drain of the second n-channel transistor, and one of a source or a drain of the second p-channel transistor,
the other of the source or the drain of the fourth n-channel transistor being connected to the sense amplifier,
a first reference potential being applicable to the other of the source or the drain of the first p-channel transistor and the other of the source or the drain of the second p-channel transistor,
a second reference potential being applied to the other of the source or the drain of the first n-channel transistor and the other of the source or the drain of the second n-channel transistor.
4. A semiconductor memory device, comprising:
a sense amplifier;
the data latch circuit according to claim 1 ,
a plurality of electrode films stacked to be separated from each other;
a semiconductor member piercing the plurality of electrode films;
a charge storage member provided between the semiconductor member and the electrode films;
a source line connected to the semiconductor member; and
a bit line connected between the semiconductor member and the sense amplifier.
5. The device according to claim 4 , wherein
the sense amplifier and the data latch circuit are provided on a first substrate,
the plurality of electrode films, the semiconductor member, the charge storage member, the source line, and the bit line are provided on a second substrate, and
the first substrate and the second substrate are bonded to each other.
6. A semiconductor memory device, comprising:
a first sense amplifier circuit; and
a second sense amplifier circuit,
the first sense amplifier circuit and the second sense amplifier circuit each including a data latch circuit including an n-channel transistor,
a gate of the n-channel transistor of the first sense amplifier circuit and a gate of the n-channel transistor of the second sense amplifier circuit being a common gate,
wherein the n-channel transistor of the first sense amplifier circuit and the n-channel transistor of the second sense amplifier circuit are transfer gates.
7. The device according to claim 6 , further comprising:
a plurality of electrode films stacked to be separated from each other;
a semiconductor member piercing the plurality of electrode films;
a charge storage member provided between the semiconductor member and the electrode films;
a source line connected to the semiconductor member; and
a bit line connecting the semiconductor member to the first sense amplifier circuit and the second sense amplifier circuit.
8. The device according to claim 7 , wherein
the first sense amplifier circuit and the second sense amplifier circuit are formed on a first substrate,
the plurality of electrode films, the semiconductor member, the charge storage member, the source line, and the bit line are formed on a second substrate, and
the first substrate and the second substrate are bonded to each other.