Radiofrequency carrier tracking for amplitude-modulated signals with an unstable reference clock
Techniques are described for accurate tracking of a radiofrequency (RF) carrier for amplitude-modulated signals in unstable reference clock environments. For example, some embodiments operate in context of clock circuits in devices configured for near-field communication (NFC) card emulation (CE) mode. The clock circuits seek to generate an internal clocking signal by tracking a clock reference, such as an RF carrier. In some cases, the clock reference can unpredictably become unreliable for periods of time, during which continued tracking of the unreliable clock reference can yield appreciable frequency and phase errors in the generated internal clocking signal. Embodiments implement phase delta detection with time limiting to limit the magnitude of such errors in the internal clocking signal introduced while tracking an unreliable clock reference. For example, embodiments force gating of phase tracking signals to limit their duration, thereby limiting impacts of those phase tracking signals on the clock circuit output.
1. A time limiter circuit for integration with a phase detector of a phase-locked loop (PLL), the time limiter circuit comprising:
an absolute phase detection sub-circuit to detect whether a phase tracking signal is asserted by the phase detector, the phase tracking signal indicating a detected phase difference between an output signal of the PLL and an input reference signal of the PLL;
a delay timer sub-circuit, coupled with the absolute phase detection sub-circuit to determine, automatically responsive to the absolute phase detection sub-circuit detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration; and
a pulse gating sub-circuit, coupled with the delay timer sub-circuit to force de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to the delay timer sub-circuit determining that the signal duration exceeds the threshold duration.
2. The time limiter circuit of claim 1 , further comprising:
an enable input node to receive a time-delay enable signal,
wherein the pulse gating sub-circuit is to force the de-assertion only when the time-delay enable signal is asserted.
3. The time limiter circuit of claim 1 , wherein:
the absolute phase detection sub-circuit is to generate an absolute phase signal responsive to detecting that the phase tracking signal is asserted by the phase detector;
the delay timer sub-circuit is to generate a gate trigger signal automatically responsive to determining that the signal duration exceeds the threshold duration based on the absolute phase signal; and
the pulse gating sub-circuit is to generate a time-limited tracking signal, such that a duration of the time-limited tracking signal is limited by the pulse gating sub-circuit forcing the de-assertion responsive to the gate trigger when the signal duration exceeds the threshold duration, and is limited by the duration of the phase tracking signal otherwise.
4. The time limiter circuit of claim 3 , wherein:
the phase tracking signal is one of an up signal or a down signal, such that assertion of the up signal increases current injection into a loop filter of the PLL, and assertion of the down signal decreases current injection into the loop filter; and
the absolute phase detection sub-circuit is to generate the absolute phase signal such that the absolute phase signal is asserted responsive to up signal being asserted and/or the down signal being asserted.
5. The time limiter circuit of claim 1 , wherein the delay timer sub-circuit comprises:
a control input node to receive a duration adjustment signal; and
a plurality of delay elements controllable according to the duration adjustment signal to adjust the threshold duration.
6. The time limiter circuit of claim 1 , wherein the delay timer sub-circuit comprises:
a reset node to receive a reset signal; and
one or more delay elements to set the threshold duration, wherein the one or more delay elements are reset according to the reset signal prior to determining whether the signal duration exceeds the set threshold duration.
7. A phase-locked loop (PLL) circuit comprising:
a PLL input node to receive a reference clock signal;
a PLL output node to output a generated clock signal; and
a phase detector, coupled with the PLL input node and the PLL output node to generate a phase tracking signal indicating a phase difference between the reference clock signal and the generated clock signal, the phase tracking signal comprising a first phase tracking signal responsive to a phase of the reference clock signal preceding a phase of the generated clock signal, and a second phase tracking signal responsive to the phase of the generated clock signal preceding the phase of the reference clock signal, the phase detector having a time limiter circuit comprising:
an absolute phase detection sub-circuit to detect whether the phase tracking signal is asserted by the phase detector;
a delay timer sub-circuit, coupled with the absolute phase detection sub-circuit to determine, automatically responsive to the absolute phase detection sub-circuit detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration; and
a pulse gating sub-circuit, coupled with the delay timer sub-circuit to force de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to the delay timer sub-circuit determining that the signal duration exceeds the threshold duration.
8. The PLL circuit of claim 7 , wherein the time-limiter circuit further comprises:
an enable input node to receive a time-delay enable signal,
wherein the pulse gating sub-circuit is to force the de-assertion only when the time-delay enable signal is asserted.
9. The PLL circuit of claim 7 , wherein:
the absolute phase detection sub-circuit is to generate an absolute phase signal responsive to detecting that the phase tracking signal is asserted by the phase detector;
the delay timer sub-circuit is to generate a gate trigger signal automatically responsive to determining that the signal duration exceeds the threshold duration based on the absolute phase signal; and
the pulse gating sub-circuit is to generate a time-limited tracking signal, such that a duration of the time-limited tracking signal is limited by the pulse gating sub-circuit forcing the de-assertion responsive to the gate trigger when the signal duration exceeds the threshold duration, and is limited by the duration of the phase tracking signal otherwise.
10. The PLL circuit of claim 9 , further comprising:
a loop filter, coupled with the phase detector, such that assertion of the first phase tracking signal increases current injection into a loop filter of the PLL, and assertion of the second phase tracking signal decreases current injection into the loop filter.
11. The PLL circuit of claim 7 , wherein the delay timer sub-circuit comprises:
a control input node to receive a duration adjustment signal; and
a plurality of delay elements controllable according to the duration adjustment signal to adjust the threshold duration.
12. The PLL circuit of claim 7 , wherein the delay timer sub-circuit comprises:
a reset node to receive a reset signal; and
one or more delay elements to set the threshold duration, wherein the one or more delay elements are reset according to the reset signal prior to determining whether the signal duration exceeds the set threshold duration.
13. The PLL circuit of claim 7 , wherein:
the reference clock signal is an amplitude shift key (ASK) modulated radiofrequency carrier signal.
14. A portable electronic device having the PLL circuit of claim 7 integrated therein, wherein:
the portable electronic device is associated with stored data and comprises an active load modulation circuit configured to generate a response signal based on active load modulation of the generated clock signal in accordance with a near field communication (NFC) card emulation (CE) mode of operation.
15. A method comprising:
detecting whether a phase tracking signal is asserted by a phase detector of the phase-locked loop (PLL), the phase tracking signal indicating a detected phase difference between an output signal of the PLL and an input reference signal of the PLL;
determining, automatically responsive to detecting that the phase tracking signal is asserted, whether a signal duration of the phase tracking signal exceeds a threshold duration; and
forcing de-assertion of the phase tracking signal for at least a remainder of a present operating cycle of the PLL automatically responsive to determining that the signal duration exceeds the threshold duration.
16. The method of claim 15 , further comprising, for each of the plurality of operating cycles:
determining whether a time-delay enable signal is asserted,
wherein the forcing de-assertion is performed only when the time-delay enable signal is asserted.
17. The method of claim 15 , wherein:
the phase tracking signal is one of an up signal or a down signal;
assertion of the up signal increases current injection into a loop filter of the PLL; and
assertion of the down signal decreases current injection into the loop filter.
18. The method of claim 15 , further comprising, for each of the plurality of operating cycles:
determining the threshold duration according to a duration adjustment signal,
wherein the threshold duration is adjustable by the duration adjustment signal.
19. The method of claim 15 , further comprising, for each of the plurality of operating cycles:
resetting a delay timer prior to the detecting, the delay timer performing the determining.
20. The method of claim 15 , wherein:
the input reference signal of the PLL is an amplitude shift key (ASK) modulated radiofrequency carrier signal.