24 to 30GHz wide band CMOS power amplifier with turn-off mode high impedance

1. A wide band matching network for power amplifier impedance matching, the wide band matching network comprising:

a power amplifier transistor connected to an output network;

the output network including:

a series capacitor;

an on-chip transformer connected to the capacitor in series, wherein the transformer and the capacitor act as a second order filter; and

an antenna port connected to the capacitor and a receiver switch,

wherein the series capacitor, the receiver switch, and the antenna port are connected at a common node.

2. The wide band matching network of claim 1 , wherein when the power amplifier is turned on and the receiver is turned off, the output network performs power amplifier matching.

3. The wide band matching network of claim 1 , wherein when the power amplifier is turned off and the receiver is turned on, the output network acts as impedance.

4. The wide band matching network of claim 1 , wherein the on-chip transformer is derived from an ideal second order filter, wherein an ideal series capacitor within the second order filter is represented as a first ideal capacitor and a second ideal capacitor, wherein the first ideal capacitor is converted to the series capacitor and the second ideal capacitor is converted to a parasitic capacitor of the on-chip transformer.

5. The wide band matching network of claim 1 , wherein ideal inductors of an ideal second order filter are converted to parasitic inductors of the on-chip transformer.

6. The wide band matching network of claim 1 , wherein ideal capacitors of an ideal second order filter are converted to parasitic capacitors of the on-chip transformer and parasitic of power amplifier transistor.

7. The wide band matching network of claim 1 , wherein ideal resistors in an ideal second order filter are converted to parasitic resistors of power amplifier transistor.

8. The wide band matching network of claim 1 , wherein the output network comprises a power amplifier balun, wherein the power amplifier balun and the series capacitor act as a transmitter.

9. A method for operating a power amplifier network, the method comprising:

determining whether to operate the power amplifier network in a power amplifier on/receiver-off mode or a power amplifier-off/receiver-on mode;

when the power amplifier-on/receiver-off mode is selected, ensuring the power amplifier is on and a receiver switch is off, and performing power amplifier impedance matching; and

when the power amplifier-off/receiver-on mode is selected, ensuring the power amplifier is off and the receiver switch is on, wherein the power amplifier network acts as impedance to prevent signal from entering the power amplifier network.

10. The method of claim 9 , wherein the power amplifier network comprises an on-chip transformer that is derived from an ideal second order filter, wherein an ideal series capacitor within the second order filter is represented as a first ideal capacitor and a second ideal capacitor, wherein the first ideal capacitor is converted to the series capacitor and the second ideal capacitor is converted to a parasitic capacitor of the on-chip transformer.

11. The method of claim 9 , wherein the power amplifier network comprises an on-chip transformer in which ideal inductors of an ideal second order filter are converted to parasitic inductors.

12. The method of claim 9 , wherein the power amplifier network comprises an on-chip transformer in which ideal capacitors of an ideal second order filter are converted to parasitic capacitors.

13. The method of claim 9 , wherein the power amplifier network comprises an on-chip transformer in which ideal resistors of an ideal second order filter are converted to parasitic resistors.

14. The method of claim 9 , wherein the power amplifier network comprises a power amplifier balun and a series capacitor, wherein the power amplifier balun and the series capacitor act as a transmitter.

15. A system for operating a power amplifier network, the system comprising:

a processor; and

a memory storing non-transitory processor-executable instructions that, when executed by the processor, cause the processor to:

determine whether to operate the power amplifier network in a power amplifier on/receiver-off mode or a power amplifier-off/receiver-on mode;

when the power amplifier-on/receiver-off mode is selected, ensure the power amplifier is on and a receiver switch is off, and perform power amplifier impedance matching; and

when the power amplifier-off/receiver-on mode is selected, ensure the power amplifier is off and the receiver switch is on, wherein the power amplifier network acts as impedance to prevent signal from entering the power amplifier network.

16. The system of claim 15 , wherein the power amplifier network comprises an on-chip transformer that is derived from an ideal second order filter, wherein an ideal series capacitor within the second order filter is represented as a first ideal capacitor and a second ideal capacitor, wherein the first ideal capacitor is converted to the series capacitor and the second ideal capacitor is converted to a parasitic capacitor of the on-chip transformer.

17. The system of claim 15 , wherein the power amplifier network comprises an on-chip transformer in which ideal inductors of an ideal second order filter are converted to parasitic inductors.

18. The system of claim 15 , wherein the power amplifier network comprises an on-chip transformer in which ideal capacitors of an ideal second order filter are converted to parasitic capacitors.

19. The system of claim 15 , wherein the power amplifier network comprises an on-chip transformer in which ideal resistors of an ideal second order filter are converted to parasitic resistors.

20. The system of claim 15 , wherein the power amplifier network comprises a power amplifier balun and a series capacitor, wherein the power amplifier balun and the series capacitor act as a transmitter.