Tiered error correction code (ECC) operations in memory
Apparatuses and methods for performing an error correction code (ECC) operation are provided. One example method can include performing a first error code correction (ECC) operation on a portion of data, performing a second ECC operation on the portion of data in response to the first ECC operation failing, and performing a third ECC operation on the portion of data in response to the second ECC operation failing.
1. A method, comprising:
performing a first error code correction (ECC) operation on data read from a memory array, wherein the first ECC operation uses hard data to correct errors in the data; and
performing a second ECC operation on the data in response to the first ECC operation failing, wherein the second ECC operation uses hard data or soft data to correct errors in the data and wherein performing the second ECC operation includes performing ECC operations on codewords that failed the first ECC operations and include changed bits from a bit flip candidate list based on a log likelihood ratio.
2. The method of claim 1 , wherein performing the second ECC operation includes using an iterative product code decoder or an outer BCH decoder on codewords that have been changed in response to the codewords failing the first ECC operation.
3. The method of claim 1 , wherein performing the first ECC operation includes performing an operation using an inner code decode and an outer code decode.
4. The method of claim 1 , wherein performing the first ECC operation includes using codewords associated with an outer code along with a block-wise concatenated codeword associated with an inner code used in the second ECC operation.
5. The method of claim 1 , wherein performing the second ECC operation includes generating the bit flip candidate list that includes bits at an intersection of a row codeword and a column codeword that failed the first ECC operation based on the log likelihood ratio.
6. The method of claim 1 , further comprising performing additional ECC operations on codewords in response to the second ECC operation failing and include changed bits from the bit flip candidate list until one of the additional ECC operations is successful or until a threshold number of additional ECC operations are performed.
7. An apparatus, comprising:
a memory device;
a controller coupled to the memory device configured to:
perform a first number of error code correction (ECC) operations on data, wherein the first number of ECC operations use hard data to correct errors in the data; and
perform a second number of ECC operations in response to the first number of ECC operations failing, wherein the second number of ECC operations use soft data to correct errors in the data, wherein the second number of ECC operations include changed bits from a bit flip candidate list based on a log likelihood ratio.
8. The apparatus of claim 7 , wherein the controller is configured to perform the second number of ECC operations on codewords that failed first number of ECC operations and wherein the second number of ECC operations include changed bits from the bit flip candidate list selected based on the log likelihood ratio until one of the second number of ECC operations is successful or until a threshold number of second number of ECC operations are performed.
9. The apparatus of claim 7 , wherein the controller is configured to perform another of the previous first number of ECC operations or second number of ECC operations on data in response to one of the second number of ECC operations failing.
10. The apparatus of claim 7 , wherein the second number of ECC operations include generating the bit flip candidate list using log likelihood ratio masking, wherein the bit flip candidate list includes bits from intersections of component codewords that failed the first number of ECC operations.
11. The apparatus of claim 7 , wherein the first number of ECC operations use hard data in a component code word to correct errors in the data.
12. The apparatus of claim 7 , wherein the first number of ECC operations use an inner code decode on the data in response to one of the first number of ECC operations failing.
13. The apparatus of claim 7 , wherein the first number of ECC operations use an inner code decode and an outer code decode in response to one of the first number of ECC operations failing.
14. A method, comprising:
performing a first number of error code correction (ECC) operations on data read from a memory array, wherein the first number of ECC operations use hard data to correct errors in the data; and
performing a second number of ECC operations on the data comprising creating a list of bit flip candidates in response to the first number of ECC operations failing to an error occurring at one or more intersections of column codewords and row codewords, further comprising creating the list of bit flip candidates using bit flip candidates selected based on a log likelihood ratio from bits at the one or more intersections of the row codewords and column codewords where an error remains.
15. The method of claim 14 , further comprising flipping a particular number of bits from the bit flip candidate list and performing the second number of ECC operations comprise using the flipped particular number of bits.
16. The method of claim 14 , wherein performing the first number of ECC operations includes using hard data in a component code word to correct errors in the data.
17. The method of claim 14 , wherein performing the first number of ECC operations includes using an inner code decode and an outer code decode to correct errors in the data.