Identification and caching of frequent read disturb aggressors

1. A method comprising:

receiving a read operation directed to an aggressor location;

performing an integrity scan of a victim location of the aggressor location to determine an error value for the victim location; and

copying data from the aggressor location to a cache in response to determining the error value for the victim location satisfies a first error value threshold, wherein the cache is a different type of memory from the aggressor location.

2. The method of claim 1 , wherein the copying the data to the cache is further in response to determining that the error value for the victim location does not satisfy a second error value threshold, wherein data is migrated to another location when the second error value threshold is satisfied.

3. The method of claim 1 , the receiving of the read operation further comprising:

receiving a plurality of read operations, the plurality of read operations divided into a current set of read operations and one or more subsequent sets of read operations; and

selecting the read operation from the current set as the aggressor location for the current set, wherein the integrity scan is performed in response to selecting the read operation as the aggressor location.

4. The method of claim 3 , further comprising:

selecting the read operation from a subsequent set as the aggressor location for the subsequent set; and

in response to determining the data from the aggressor location is in the cache, foregoing performance of an integrity scan for the subsequent set.

5. The method of claim 1 , wherein the cache is a single-level cell portion of memory reserved for cache aggressor location data and wherein the aggressor location is a portion of memory that has greater bit density than the single-level cell portion of memory.

6. The method of claim 1 , the copying of data to the cache comprising:

determining the cache is full;

selecting a cache entry having a lowest victim error value of entries in the cache; and

evicting the selected cache entry.

7. The method of claim 1 , further comprising:

receiving a subsequent read operation directed to the aggressor location; and

in response to determining the data from the aggressor location is in the cache, fulfilling the read operation using the data from the aggressor location in the cache.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:

receive a read operation directed to an aggressor location;

perform an integrity scan of a victim location of the aggressor location to determine an error value for the victim location; and

copy data from the aggressor location to a cache in response to determining the error value for the victim location satisfies a first error value threshold, wherein the cache is a different type of memory from the aggressor location.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the copying the data to the cache is further in response to determining that the error value for the victim location does not satisfy a second error value threshold, wherein data is migrated to another location when the second error value threshold is satisfied.

10. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

receive a plurality of read operations, the plurality of read operations divided into a current set of read operations and one or more subsequent sets of read operations; and

select the read operation from the current set as the aggressor location for the current set, wherein the integrity scan is performed in response to selecting the read operation as the aggressor location.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the processing device is further to:

select the read operation from a subsequent set as the aggressor location for the subsequent set; and

in response to determining the data from the aggressor location is in the cache, forego performance of an integrity scan for the subsequent set.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the cache is a single-level cell portion of memory reserved for cache aggressor location data and wherein the aggressor location is a portion of memory that has greater bit density than the single-level cell portion of memory.

13. The non-transitory computer-readable storage medium of claim 8 , the copying of data to the cache comprising:

determining the cache is full;

selecting a cache entry having a lowest victim error value of entries in the cache; and

evicting the selected cache entry.

14. The non-transitory computer-readable storage medium of claim 8 , wherein the processing device is further to:

receive a subsequent read operation directed to the aggressor location; and

in response to determining the data from the aggressor location is in the cache, fulfill the read operation using the data from the aggressor location in the cache.

15. A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to:

receive a plurality of read operations, the plurality of read operations divided into a current set of read operations and one or more subsequent sets of read operations;

select the read operation from the current set as an aggressor location for the current set;

perform an integrity scan of a victim location of the aggressor location to determine an error value for the victim location, wherein the integrity scan is performed in response to selecting the read operation as the aggressor location; and

copy data from the aggressor location to a cache in response to determining the error value for the victim location satisfies a first error value threshold, wherein the cache is a different type of memory from the aggressor location.

16. The system of claim 15 , wherein the copying the data to the cache is further in response to determining that the error value for the victim location does not satisfy a second error value threshold, wherein data is migrated to another location when the second error value threshold is satisfied.

17. The system of claim 15 , wherein the processing device is further to:

select the read operation from a subsequent set as the aggressor location for the subsequent set; and

in response to determining the data from the aggressor location is in the cache, forego performance of an integrity scan for the subsequent set.

18. The system of claim 15 , wherein the cache is a single-level cell portion of memory reserved for cache aggressor location data and wherein the aggressor location is a portion of memory that has greater bit density than the single-level cell portion of memory.

19. The system of claim 15 , the copying of data to the cache comprising:

determining the cache is full;

selecting a cache entry having a lowest victim error value of entries in the cache; and

evicting the selected cache entry.

20. The system of claim 15 , wherein the processing device is further to:

receive a subsequent read operation directed to the aggressor location; and

in response to determining the data from the aggressor location is in the cache, fulfill the read operation using the data from the aggressor location in the cache.