Common rail contact
A method according to the present disclosure includes receiving a workpiece including a gate structure, a first source/drain (S/D) feature, a second S/D feature, a first dielectric layer over the gate structure, the first S/D feature, the second S/D feature, a first S/D contact over the first S/D feature, a second S/D contact over the second S/D feature, a first etch stop layer (ESL) over the first dielectric layer, and a second dielectric layer over the first ESL, forming a S/D contact via through the second dielectric layer and the first ESL to couple to the first S/D contact, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure, and forming a common rail opening adjoining the gate contact opening to expose the second S/D contact, and forming a common rail contact in the common rail opening.
1. A method, comprising:
receiving a workpiece comprising:
a gate structure,
a first source/drain feature and a second source/drain feature,
a first dielectric layer over the gate structure, the first source/drain feature and the second source/drain feature,
a first source/drain contact disposed over the first source/drain feature,
a second source/drain contact disposed over the second source/drain feature,
a first etch stop layer (ESL) over the first dielectric layer, and
a second dielectric layer over the first ESL;
forming a source/drain contact via through the second dielectric layer and the first ESL to couple to the first source/drain contact, the forming of the source/drain contact via comprising:
etching the first ESL and the second dielectric layer to form a source/drain contact via opening to expose the first source/drain contact,
recessing the first source/drain contact to extend the source/drain contact via opening into the first source/drain contact such that the source/drain contact via opening undercuts the first ESL,
after the recessing, depositing a metal fill layer into the source/drain contact via opening,
after the depositing of the metal fill layer, performing a first implantation process to implant a semiconductor dopant,
after the performing of the first implantation process, depositing a glue layer over the metal fill layer, and
depositing a buffer layer over the glue layer;
after the forming of the source/drain contact via, forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure;
after the forming of the gate contact opening, forming a common rail opening adjoining the gate contact opening, wherein the second source/drain contact is exposed in the common rail opening; and
after the forming the common rail opening, forming a common rail contact in the common rail opening.
2. The method of claim 1 , wherein the forming of the source/drain contact via further comprises:
after the depositing of the buffer layer, planarizing the workpiece to remove the glue layer and the buffer layer.
3. The method of claim 2 , wherein the forming of the source/drain contact via further comprises:
after the planarizing, performing a second implantation process to implant the semiconductor dopant.
4. The method of claim 1 , wherein the semiconductor dopant comprises germanium.
5. The method of claim 1 , wherein the glue layer comprises titanium or titanium nitride.
6. The method of claim 1 , wherein the buffer layer comprises tungsten.
7. The method of claim 1 , wherein the depositing of the metal fill layer and the depositing of the buffer layer are performed using different deposition processes.
8. The method of claim 1 , wherein the metal fill layer is deposited into the source/drain contact via opening in a bottom-up manner such that the deposited metal fill layer comprises a mushroom-like top that rises above the first ESL.
9. A method, comprising:
receiving a workpiece comprising:
a gate structure,
a first source/drain feature adjacent the gate structure,
a first dielectric layer over the gate structure and the first source/drain feature,
a first source/drain contact disposed over the first source/drain feature,
a first etch stop layer (ESL) over the first dielectric layer, and
a second dielectric layer over the first ESL;
forming a gate contact opening through the second dielectric layer, the first ESL, and the first dielectric layer to expose the gate structure;
after the forming of the gate contact opening, forming a common rail opening adjoining the gate contact opening, wherein the first source/drain contact is exposed in the common rail opening, the forming of the common rail opening comprising:
forming a patterned photoresist layer over the second dielectric layer, the patterned photoresist layer comprising an opening direct over the first source/drain contact and the gate contact opening;
etching the first ESL and the second dielectric layer using a first dry etch process and the patterned photoresist layer as an etch mask, wherein the first source/drain contact remains covered by a portion of the first ESL; and
after the etching, cleaning the common rail opening using a first wet clean process;
after the cleaning, performing a second dry etch process to remove the portion of the first ESL and to expose the first source/drain contact; and
after the forming the common rail opening, forming a common rail contact in the common rail opening.
10. The method of claim 9 ,
wherein the forming of the common rail opening further comprises:
after the performing the second dry etch process, performing a second wet clean process.
11. The method of claim 10 , wherein the second dry etch process is different from the first dry etch process.
12. The method of claim 10 ,
wherein the first dry etch process comprises use of hydrocarbons or fluorinated hydrocarbons,
wherein the second dry etch process comprises use of nitrogen or hydrogen.
13. The method of claim 9 , wherein the forming of the common rail contact comprises:
cleaning the common rail opening;
depositing a glue layer over the common rail opening;
depositing a metal nucleation layer over the glue layer; and
depositing a metal fill layer over the metal nucleation layer.
14. The method of claim 13 , wherein the depositing of the glue layer comprises:
depositing a titanium layer over the common rail opening using physical vapor deposition (PVD); and
after the depositing of the titanium layer, depositing a titanium nitride layer using chemical vapor deposition (CVD).
15. The method of claim 9 , further comprising:
before the forming of the gate contact opening, etching the first ESL and the second dielectric layer to form a source/drain contact via opening to expose the first source/drain contact;
recessing the first source/drain contact to extend the source/drain contact via opening into the first source/drain contact such that the source/drain contact via opening undercuts the first ESL; and
after the recessing, depositing a metal fill layer into the source/drain contact via opening.
16. A semiconductor structure, comprising:
a gate structure disposed over a channel region of a first fin structure;
a first source/drain feature disposed over a source/drain region of the first fin structure adjacent the gate structure;
a second source/drain feature disposed over a source/drain region of a second fin structure different from the first fin structure;
a contact etch stop layer (CESL) over the first source/drain feature and the second source/drain feature;
a bottom dielectric layer disposed over the CESL;
a capping layer disposed over top surfaces of the gate structure, the first source/drain feature, the second source/drain feature, the CESL, and the bottom dielectric layer;
a first dielectric layer over the capping layer;
a first etch stop layer (ESL) over the first dielectric layer;
a second dielectric layer over the first ESL;
a first source/drain contact disposed over the first source/drain feature and extending through the first dielectric layer, the capping layer, the bottom dielectric layer, and the CESL;
a second source/drain contact that extends through the first dielectric layer, the capping layer, the bottom dielectric layer, and the CESL to come in contact with the second source/drain feature;
a source/drain contact via that extends through the first ESL and the second dielectric layer to come in contact with the second source/drain contact; and
a common rail contact extending through the second dielectric layer, the first ESL, the first dielectric layer, and the capping layer to come in contact with the gate structure,
wherein a portion of the common rail contact is disposed on a top surface of the first source/drain contact,
wherein top surfaces of the source/drain contact via and the common rail contact are coplanar.
17. The semiconductor structure of claim 16 , wherein the common rail contact spans over the first source/drain contact and the gate structure.
18. The semiconductor structure of claim 16 ,
wherein the first source/drain contact comprises cobalt,
wherein the common rail contact comprises a glue layer and a metal fill layer,
wherein the glue layer comprises a titanium layer and a titanium nitride layer,
wherein the metal fill layer comprises tungsten.
19. The semiconductor structure of claim 16 ,
wherein the source/drain contact via extends into the second source/drain contact,
wherein a portion of the source/drain contact via undercuts the first ESL.
20. The semiconductor structure of claim 19 ,
wherein the first fin structure and the second fin structure extends lengthwise along a first direction,
wherein the source/drain contact via is spaced apart from the common rail contact along a second direction perpendicular to the first direction by the first ESL and the second dielectric layer.