IP Library › Granted Patent US 11,848,240
Granted Patent B2
US 11,848,240 · App. 17/114,082 · Granted Dec 19, 2023

Method of manufacturing a semiconductor device

Inventors: Shu-Uei Jang (Hsinchu, TW); Chen-Huang Huang (Shuishang Township, TW); Ryan Chia-Jen Chen (Chiayi, TW); Shiang-Bau Wang (Pingzchen, TW); Shu-Yuan Ku (Zhubei, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H01L21/823431H01L21/0337H01L21/3086H01L21/76224H01L21/823437H01L21/823468H01L27/0886H01L29/6653H01L29/66545H01L29/66795H01L29/785
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Quick Facts
Patent No.
US 11,848,240
App. No.
17/114,082
Granted
Dec 19, 2023
Kind
B2
Abstract

A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

Claims (44)

1. A method of manufacturing a semiconductor device, the method comprising:

etching a metal gate into a first metal gate and a second metal gate, wherein after the etching the metal gate, an oxide is present on a first sidewall of the first metal gate;

removing the oxide from the first sidewall of the first metal gate; and

capping a void adjacent to a second sidewall of the first metal gate to form a gaseous spacer.

2. The method of claim 1 , further comprising removing a spacer from the second sidewall of the first metal gate after the removing the oxide from the first sidewall, the removing the spacer creating the void.

3. The method of claim 1 , wherein the removing the oxide is performed at least in part with a mixture of hydrogen fluoride and ammonia.

4. The method of claim 3 , wherein the mixture of the hydrogen fluoride and ammonia has a mixture flow ratio of between 1:5 and 5:1.

5. The method of claim 4 , wherein the removing the oxide further comprises an annealing process.

6. The method of claim 5 , wherein the annealing process is performed at a temperature of between 100° C. and 200° C.

7. The method of claim 1 , wherein the removing the oxide forms (NH 4 ) 2 SiF 6 .

8. A method of manufacturing a semiconductor device, the method comprising:

removing a portion of a gate stack over a semiconductor fin, wherein the removing the portion of the gate stack is performed with a cyclical etching process to form an opening, the cyclical etching process leaving an oxide material along sidewalls of the opening;

removing the oxide material from along the sidewalls of the opening;

after the removing the oxide material, filling the opening with a dielectric material;

removing spacers adjacent to the gate stack to form a void; and

capping the void to form an air spacer adjacent to the gate stack.

9. The method of claim 8 , wherein the removing the oxide material comprises:

reacting the oxide material to form a first intermediate material; and

removing the first intermediate material.

10. The method of claim 9 , wherein the removing the first intermediate material is performed at least in part with an annealing process.

11. The method of claim 10 , wherein the annealing process is performed at a temperature of between 100° C. and 200° C.

12. The method of claim 8 , wherein each cycle of the cyclical etching process comprises:

depositing a liner material;

etching through the liner material; and

using the liner material as a mask to etch the gate stack.

13. The method of claim 8 , further comprising after the filling the opening with the dielectric material, recessing an interlayer dielectric to form a recess.

14. The method of claim 13 , further comprising filling the recess with a second dielectric material.

15. A method of manufacturing a semiconductor device, the method comprising:

forming an opening in a layer over a conductive gate over a semiconductor fin;

depositing a first liner in the opening;

etching a first bottom of the first liner;

etching the conductive gate after the etching the first bottom;

depositing a second liner within the opening;

etching a second bottom of the second liner;

etching the conductive gate after the etching the second bottom;

removing an oxide from a sidewall of the conductive gate after the etching the conductive gate after the etching the second bottom;

filling the opening with a dielectric material;

after the filling the opening, removing spacers from adjacent to the conductive gate to form a void; and

capping the void to form air spacers.

16. The method of claim 15 , wherein the removing the oxide from the sidewall is performed at least in part with a mixture of hydrogen fluoride and ammonia, the mixture having a flow ratio of hydrogen fluoride to ammonia of between 1:5 and 5:1.

17. The method of claim 16 , wherein the removing the oxide further comprises an annealing process.

18. The method of claim 17 , wherein the first liner has a thickness of between 2 nm and 4 nm.

19. The method of claim 18 , wherein the removing the oxide is performed at a pressure of between 1.5 Torr and 2 Torr.

20. The method of claim 19 , wherein the removing the oxide forms (NH 4 ) 2 SiF 6 .

Continuity (3)
Continuation 16400418 · May 1, 2019
Provisional Application 62773716 · Nov 30, 2018
Related Publication 20210090958A1 · Mar 25, 2021