Sidewall passivation for HEMT devices
Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer is a first III-nitride material and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and is a second III-nitride material. Source and drain regions are arranged over the ternary III/V semiconductor layer. A gate structure is arranged over the heterojunction structure and arranged between the source and drain regions. The gate structure is a third III-nitride material. A first passivation layer directly contacts an entire sidewall surface of the gate structure and is a fourth III-nitride material. The entire sidewall surface has no dangling bond. A second passivation layer is conformally disposed along the first passivation layer, the second passivation layer has no physical contact with the gate structure.
1. A high electron mobility transistor (HEMT), comprising:
a heterojunction structure arranged over a semiconductor substrate, the heterojunction structure comprising: a binary III/V semiconductor layer being a first III-nitride material to act as a channel region of the HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and being a second III-nitride material to act as a barrier layer;
source and drain regions arranged over the ternary III/V semiconductor layer and spaced apart laterally from one another;
a gate structure arranged over the heterojunction structure and arranged between the source and drain regions, wherein the gate structure is a third III-nitride material;
a first passivation layer directly contacting an entire sidewall surface of the gate structure and being a fourth III-nitride material, the entire sidewall surface having no dangling bond; and
a second passivation layer conformally disposed along the first passivation layer, wherein the second passivation layer has no physical contact with the gate structure.
2. The HEMT of claim 1 ,
wherein the fourth III-nitride material is aluminum nitride or boron nitride, and wherein the second conformal passivation layer is silicon dioxide or silicon nitride,
wherein the first passivation layer is configured to reduce a number of traps on the entire sidewall surface of the gate structure.
3. The HEMT of claim 1 , wherein the third III-nitride material of the gate structure is a binary III/V semiconductor material having a same binary semiconductor constituents as the first III-nitride material, and the fourth III-nitride material of the first passivation layer is a binary III/V semiconductor material having different binary semiconductor constituents from the first and second III-nitride materials.
4. The HEMT of claim 1 , wherein the gate structure is doped n-type or p-type, and wherein the binary III/V semiconductor layer is an intrinsic semiconductor material.
5. The HEMT of claim 1 , wherein the first passivation layer is conformal and has a first thickness in a range of of between 5 Angstroms and 500 Angstroms.
6. The HEMT of claim 5 ,
wherein the second passivation layer has a second thickness in a range of 50 nm to 500 nm;
wherein a minimum value of the second thickness is 100 times a minimum value of the first thickness; and
wherein a material composition of the second passivation layer is different from a material composition of the first passivation layer.
7. The HEMT of claim 1 , further comprising:
one or more buffer layers under the binary III/V semiconductor layer, wherein an uppermost buffer layer is the second III-nitride material and wherein a lower buffer layer under the uppermost buffer layer is the fourth III-nitride material.
8. The HEMT of claim 7 , wherein the first passivation layer is a same material as the lower buffer layer.
9. The HEMT of claim 8 , wherein:
the first III-nitride material of the binary III/V semiconductor layer is GaN;
the second III-nitride material of the ternary III/V semiconductor layer is Al x Ga 1-x N; and
the third III-nitride material of the gate structure is n-type or p-type GaN.
10. The HEMT of claim 1 , further comprising
a capping layer conformally disposed over an upper surface region of the second passivation layer; and
a metal gate electrode including edges that overlie an upper surface region of the capping layer, and including inner sidewalls that extend downward along sidewalls of an opening through the capping layer, through the second passivation layer, and through the first passivation layer to be in direct electrical connection with an upper surface of the gate structure.
11. A method of forming an enhancement mode, high electron mobility transistor (e-HEMT) on a substrate, comprising:
forming a binary III-nitride channel layer over the substrate;
forming a ternary III-nitride barrier layer over the binary III-nitride channel layer, wherein the ternary III-nitride barrier layer meets the binary III-nitride channel layer at a heterojunction interface;
forming a binary III-nitride gate layer over the ternary III-nitride barrier layer and doping the binary III-nitride gate layer with donor or acceptor impurities;
removing selected portions of the doped binary III-nitride gate layer to form a doped binary III-nitride gate structure having an upper gate surface and outer gate sidewalls and leaving an upper surface region of the ternary III-nitride barrier layer exposed;
forming a first conformal passivation layer along the upper gate surface, the outer gate sidewalls, and the exposed upper surface region of the ternary III-nitride barrier layer, wherein the first conformal passivation layer directly contacts an entire sidewall surface of the outer gate sidewalls, and wherein the first conformal passivation layer terminates and passivates dangling bonds on the entire sidewall surface to reduces a number of traps of the outer gate sidewalls; and
forming a second conformal passivation layer over the first conformal passivation layer, the second conformal passivation layer having no physical contact with the doped binary III-nitride gate structure.
12. The method of claim 11 ,
wherein the first conformal passivation layer is aluminum nitride or boron nitride; and wherein the second conformal passivation layer is silicon dioxide or silicon nitride; and
wherein the second conformal passivation layer protects the first conformal passivation layer.
13. The method of claim 11 , wherein the first conformal passivation layer is formed by atomic layer deposition (ALD).
14. The method of claim 11 , wherein the second conformal passivation layer is formed by a different technique than the first conformal passivation layer.
15. The method of claim 14 , wherein the first conformal passivation layer is formed by atomic layer deposition (ALD) and has a thickness of between 5 angstroms and 500 angstroms, and wherein the second conformal passivation layer is formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or physical vapor deposition (PVD) and has a thickness of between 50 nm and 500 nm to protect the first conformal passivation layer during processing.
16. The method of claim 14 , further comprising:
forming a source/drain mask over the second conformal passivation layer;
performing an etch to form source/drain openings with the source/drain mask in place, wherein the source/drain openings extend through the first and second conformal passivation layers and terminate on the ternary III-nitride barrier layer; and
filling the source/drain openings with a conductive material.
17. The method of claim 16 , further comprising:
patterning the conductive material to form source/drain conductive bodies;
forming a dielectric capping layer over the source/drain conductive bodies;
forming a gate electrode mask over the dielectric capping layer;
performing an etch with the gate electrode mask in place to form a gate electrode opening which extends through the dielectric capping layer, the first conformal passivation layer, and the second conformal passivation layer, wherein the gate electrode opening terminates on the doped binary III-nitride gate structure; and
forming a conductive gate electrode liner in the gate electrode opening.
18. The method of claim 17 ,
wherein the binary III-nitride channel layer is made of GaN;
wherein the ternary III-nitride barrier layer is made of Al x Ga 1-x N;
wherein the doped binary III-nitride gate structure is n-type or p-type GaN; and
wherein the dielectric capping layer is SiN or SiO2.
19. The method of claim 14 , further comprising:
forming a first buffer layer prior to forming the binary III-nitride channel layer over the substrate; and
forming a second buffer layer over the first buffer layer prior to forming the binary III-nitride channel layer over the substrate.
20. An enhancement mode high electron mobility transistor (HEMT) formed on a substrate, comprising:
an AlN buffer layer disposed over the substrate;
an AlGaN buffer layer over the AlN buffer layer;
a GaN channel layer over the AlGaN buffer layer;
an AlGaN barrier layer over the GaN channel layer;
a GaN gate structure over the AlGaN barrier layer, wherein the GaN gate structure is doped with acceptor or donor impurities and has a gate structure upper surface and gate structure outer sidewalls;
an AlN or BN conformal passivation layer disposed over the gate structure upper surface and directly contacting an entire sidewall surface of the gate structure outer sidewalls, the entire sidewall surfaces having no dangling bond; and
a second passivation layer conformally overlying the AlN or BN conformal passivation layer, the second passivation layer having no physical contact with the GaN gate structure and has a material composition different from the AlN or BN conformal passivation layer.