Conditional direct memory access channel activation

1. A conditional direct memory access (DMA) channel activation system for executing a complex data transfer in a system-on-chip, comprising:

a look-up table constructed and arranged to store elements of an activation profile;

a trigger circuit that controls a DMA transaction according to the activation profile of the look-up table; and

a comparison circuit that performs a computer logic operation on a first operand and a second operand, wherein the trigger circuit triggers a data instruction in response to the computer logic operation.

2. The conditional DMA channel activation system of claim 1 , wherein the look-up table stores at least one of the first operand and the second operand, and a mask value for generating an activation condition.

3. The conditional DMA channel activation system of claim 1 , further comprising a linking module that links a first conditional DMA channel activation (CDCA) channel having a value stored at the look-up table to a second CDCA channel when a CDCA triggered mode allows a chain of activation conditions to be part of a triggering operation of a DMA transaction executed by the trigger circuit.

4. The conditional DMA channel activation system of claim 1 , wherein the trigger circuit activates a DMA channel or links to another CDCA channel, wherein the DMA channel is triggered to execute a copy operation from a peripheral device to a random access memory (RAM), and the CDCA channel defines an action corresponding to the activation profile in the look-up table.

5. The conditional DMA channel activation system of claim 1 , wherein the conditional DMA channel activation system operates according to the look-up table in a software mode or a triggered mode.

6. The conditional DMA channel activation system of claim 5 , wherein the triggered mode includes one of an event mode, a timer mode, or a linked mode.

7. The conditional DMA channel activation system of claim 1 , wherein the comparison circuit receives a trigger signal from a software bit, an IP flag, or another CDCA channel.

8. The conditional DMA channel activation system of claim 1 , wherein the look-up table comprises a set of fields for data entry inputs including one or more of an entry field, a domain identification field, a DMA CDCA trigger field, an address field, a mask field, a result operand field, an operation field, a DMA channel trigger field, and a conditional DMA Channel trigger field.

9. A direct memory access (DMA) controller, comprising:

a look-up table constructed and arranged to store elements of an activation profile;

a trigger circuit that controls a DMA transaction according to the activation profile of the look-up table; and

a comparison circuit that performs a computer logic operation on a first operand and a second operand, at least the second operand stored at the look-up table, which permits a value in a memory location to be processed by the trigger circuit to trigger the DMA transaction.

10. The DMA controller of claim 9 , wherein the look-up table stores at least one of the first operand and the second operand, and further stores a mask value for generating an activation condition.

11. The DMA controller of claim 9 , further comprising a linking module that links a first conditional DMA channel activation (CDCA) channel having a value stored at the look-up table to a second CDCA channel when a CDCA triggered mode allows a chain of activation conditions to be part of a triggering operation of a DMA transaction executed by the trigger circuit.

12. The DMA controller of claim 9 , wherein the trigger circuit causes a DMA channel to execute a copy operation from a peripheral device to a random access memory (RAM), and the CDCA channel defines an action corresponding to the activation profile in the look-up table.

13. The DMA controller of claim 9 , wherein the DMA controller operates according to the look-up table in a software mode or a triggered mode.

14. The DMA controller of claim 13 , wherein the triggered mode includes one of an event mode, a timer mode, or a linked mode.

15. The DMA controller of claim 9 , wherein the comparison circuit receives a trigger signal from a software bit, an IP flag, or another CDCA channel.

16. The DMA controller of claim 9 , wherein the comparison circuit performs the comparison or logic operation before triggering the trigger circuit triggers the DMA transaction so that any bit in a computer memory location is available to trigger that DMA transaction.

17. A method for activating a conditional direct memory access (DMA) channel to execute a complex data transfer, comprising:

reading, by a DMA controller, a memory location defined in a look-up table, the look-up table constructed and arranged to store elements of an activation profile;

performing, by the DMA controller, a mask or logic operation with an operand stored in the look-up table;

determining a match in response to comparing an operand modified by a mask value of the look-up table to a result operand of the look-up table; and

triggering a channel defined in the activation profile or another read compare operation in the look-up table.

18. The method of claim 17 , wherein triggering the channel includes operating according to the look-up table in a software mode or a triggered mode.

19. The method of claim 18 , wherein the triggered mode includes one of an event mode, a timer mode, or a linked mode.