Granted Patent B2

US 12,189,471 · App. 18/381,320 · Granted Jan 7, 2025

Inventor: Anand Kumar G (Bengaluru, IN)

Assignee: Texas Instruments Incorporated

G06F11/1004G06F13/28

Abstract

Claims (57)

1. An apparatus, comprising:

a direct memory access (DMA) component comprising a data buffer, wherein the DMA component is configured to:

transfer a first copy of data from a first device to the data buffer to form first stored data;

determine a first value based on the first stored data;

transfer a second copy of the data from the first device to the data buffer to form second stored data;

determine a second value based on the second stored data; and

determine a first result of data integrity validation based on the first value and the second value.

2. The apparatus of claim 1 , wherein to determine the first result of data integrity validation, the DMA component is configured to:

compare the first value to the second value to determine a comparison result indicating whether the first value matches the second value; and

determine the first result of data integrity validation based on the comparison result.

3. The apparatus of claim 1 , wherein the first value is a checksum of the first stored data, and the second value is a checksum of the second stored data.

4. The apparatus of claim 1 ,

wherein the DMA component is configured to receive a signal requesting for the data integrity validation, and

wherein the DMA component is configured to, in response to the signal, determine the first value based on the first stored data, transfer the second copy of the data from the first device to the data buffer to form the second stored data, determine the second value based on the second stored data, and determine the first result of data integrity validation based on the first value and the second value.

5. The apparatus of claim 1 , wherein the second stored data overwrites the first stored data.

6. The apparatus of claim 1 ,

wherein the first device is a memory device, or a peripheral device of the apparatus, and

wherein the peripheral device comprises a first-in first-out (FIFO) buffer, wherein a first pointer of the FIFO buffer indicates a first memory address of the FIFO buffer associated with transferring the first copy of the data from the peripheral device to the data buffer of the DMA component, and wherein a second pointer of the FIFO buffer indicates a second memory address of the FIFO buffer associated with transferring the second copy of the data from the peripheral device to the data buffer of the DMA component.

7. The apparatus of claim 1 , wherein the DMA component is configured to:

transfer one of the first or second stored data from the data buffer of the DMA component to a second device to form third stored data;

transfer a copy of the third stored data from the second device to the data buffer to form fourth stored data;

determine a third value based on the fourth stored data; and

determine a second result of data integrity validation based on the third value and one of the first or second values.

8. The apparatus of claim 7 , wherein the fourth stored data overwrites the one of the first or second stored data.

9. The apparatus of claim 7 ,

wherein the second device is a memory device, or a peripheral device of the apparatus, and

wherein the peripheral device comprises a first-in first-out (FIFO) buffer, wherein a first pointer of the FIFO buffer indicates a first memory address of the FIFO buffer associated with providing the one of the first or second stored data from the data buffer of the DMA component to the peripheral device, and wherein a second pointer of the FIFO buffer indicates a second a memory address of the FIFO buffer associated with transferring the copy of the third stored data from the peripheral device to the data buffer of the DMA component.

10. A system, comprising:

a system control component; and

a direct memory access (DMA) component coupled to and controlled by the system control component, wherein under control of the system control component, the DMA component is configured to:

transfer a first copy of data from a first device to a data buffer of the DMA component to form first stored data;

determine a first value based on the first stored data;

transfer a second copy of the data from the first device to the data buffer of the DMA component to form second stored data;

determine a second value based on the second stored data; and

determine a first result of data integrity validation based on the first value and the second value.

11. The system of claim 10 , wherein to determine the first result of data integrity validation, the DMA component is configured to:

compare the first value to the second value to determine a comparison result indicating whether the first value matches the second value; and

determine the first result of data integrity validation based on the comparison result.

12. The system of claim 10 , wherein the first value is a checksum of the first stored data, and the second value is a checksum of the second stored data.

13. The system of claim 10 ,

wherein the DMA component is configured to receive a signal requesting for the data integrity validation, and

wherein the DMA component is configured to, in response to the signal, determine the first value based on the first stored data, transfer the second copy of the data from the first device to the data buffer to form the second stored data, determine the second value based on the second stored data, and determine the first result of data integrity validation based on the first value and the second value.

14. The system of claim 10 , wherein the second stored data overwrites the first stored data.

15. The system of claim 10 ,

wherein the first device is a memory device, or a peripheral device of the system, and

wherein the peripheral device comprises a first-in first-out (FIFO) buffer, wherein a first pointer of the FIFO buffer indicates a first memory address of the FIFO buffer associated with transferring the first copy of the data from the peripheral device to the data buffer of the DMA component, and wherein a second pointer of the FIFO buffer indicates a second memory address of the FIFO buffer associated with transferring the second copy of the data from the peripheral device to the data buffer of the DMA component.

16. The system of claim 15 , wherein the peripheral device comprises an analog-to-digital converter (ADC).

17. The system of claim 10 , wherein the DMA component is configured to:

transfer one of the first or second stored data from the data buffer of the DMA component to a second device to form third stored data;

transfer a copy of the third stored data from the second device to the data buffer to form fourth stored data;

determine a third value based on the fourth stored data; and

determine a second result of data integrity validation based on the third value and one of the first or second values.

18. The system of claim 17 , wherein the fourth stored data overwrites the one of the first or second stored data.

19. The system of claim 17 ,

wherein the second device is a memory device, or a peripheral device of the system, and

wherein the peripheral device comprises a first-in first-out (FIFO) buffer, wherein a first pointer of the FIFO buffer indicates a first memory address of the FIFO buffer associated with providing the one of the first or second stored data from the data buffer of the DMA component to the peripheral device, and wherein a second pointer of the FIFO buffer indicates a second a memory address of the FIFO buffer associated with transferring the copy of the third stored data from the peripheral device to the data buffer of the DMA component.

20. The system of claim 19 , wherein the peripheral device comprises a digital-to-analog converter (ADC).

Priority Claims (1)

Continuity (2)

References Cited (10)

Cited By (1)

US 12,724,896