Semiconductor devices and methods of forming the same
A method includes providing a structure having first and second fins over a substrate and oriented lengthwise generally along a first direction and source/drain (S/D) features over the first and second fins; forming an interlayer dielectric (ILD) layer covering the S/D features; performing a first etching process at least to an area between the S/D features, thereby forming a trench in the ILD layer; depositing a dielectric material in the trench; performing a second etching process to selectively recess the dielectric material; and performing a third etching process to selectively recess the ILD layer, thereby forming a contact hole that exposes the S/D features.
1. A method of forming a semiconductor device, comprising:
providing a structure that includes a substrate, a fin protruding from the substrate, an isolation feature surrounding the fin, and a gate structure engaging the fin;
depositing a resist layer covering the fin, the isolation feature, and the gate structure;
performing a first etching process to recess the resist layer below a top surface of the gate structure;
performing a second etching process to further recess the resist layer, wherein the second etching process has a higher etching rate than the first etching process;
performing a third etching process to remove the resist layer, wherein the third etching process has a lower etching rate than the second etching process;
recessing the fin; and
forming an epitaxial source/drain (S/D) feature above the fin.
2. The method of claim 1 , wherein the recessing of the fin also includes recessing the isolation feature.
3. The method of claim 2 , wherein after the recessing of the isolation feature, a top surface of the isolation feature has a step profile.
4. The method of claim 1 , wherein each of the first, second, and third etching processes includes a plasma etching process under a bias voltage for a duration.
5. The method of claim 4 , wherein the bias voltage of the second etching process is higher than that of either the first etching process or the third etching process.
6. The method of claim 4 , wherein the duration of the second etching process is shorter than that of either the first etching process or the third etching process.
7. The method of claim 1 , wherein each of the first, second, and third etching processes uses a same etchant.
8. The method of claim 7 , wherein the etchant includes a sulfur-containing compound.
9. The method of claim 1 , wherein after the performing of the second etching process, a top surface of the resist layer is above a top surface of the fin.
10. The method of claim 1 , wherein after the performing of the second etching process, a top surface of the resist layer is below a top surface of the fin.
11. A method of forming a semiconductor device, comprising:
providing a structure that includes a substrate with a first region and a second region, an isolation feature over the substrate, a first fin extending from the first region of the substrate and through the isolation feature, a second fin extending from the second region of the substrate and through the isolation feature, and a gate structure engaging the first and second fins;
recessing the first fin and a first portion of the isolation feature surrounding the first fin;
epitaxially growing a first source/drain (S/D) feature on the first fin;
recessing the second fin and a second portion of the isolation feature surrounding the second fin, resulting in a protruding portion of the isolation feature between the first and second portions; and
epitaxially growing a second S/D feature on the second fin.
12. The method of claim 11 , further comprising:
depositing a first resist layer covering the first and second regions;
removing the first resist layer from the first region prior to the recessing of the first fin and the first portion of the isolation feature;
removing the first resist layer from the second region;
depositing a second resist layer covering the first and second regions;
removing the second resist layer from the second region prior to the recessing of the second fin and the second portion of the isolation feature; and
removing the second resist layer from the first region.
13. The method of claim 12 , wherein each of the removing of the first resist layer from the first region and the removing of the second resist layer from the second region includes:
etching an upper portion of either the first resist layer or the second resist layer with a first etching directivity; and
etching a lower portion of either the first resist layer or the second resist layer with a second etching directivity that is lower than the first etching directivity.
14. The method of claim 11 , wherein a sidewall of the protruding portion of the isolation feature is substantially perpendicular to a top surface of the isolation feature.
15. The method of claim 11 , wherein the protruding portion of the isolation feature is across a boundary line between the first and second regions.
16. The method of claim 11 , wherein the first and second S/D features are of opposite types.
17. A semiconductor device, comprising:
a substrate having a p-type region and an n-type region;
an isolation feature over the substrate;
a first fin protruding from the substrate and through the isolation feature in the p-type region;
a p-type epitaxial feature over a source/drain (S/D) region of the first fin;
a second fin protruding from the substrate and through the isolation feature in the n-type region; and
an n-type epitaxial feature over an S/D region of the second fin,
wherein a portion of the isolation feature across the p-type region and the n-type region is higher than other portions of the isolation feature.
18. The semiconductor device of claim 17 , wherein a sidewall of the portion of the isolation feature is substantially perpendicular to a top surface of the substrate.
19. The semiconductor device of claim 17 , wherein the portion of the isolation feature is higher than the first and second fins in respective S/D regions.
20. The semiconductor device of claim 17 , further comprising:
a gate stack engaging a channel region of the first fin and a channel region of the second fin.