Refresh management for DRAM
A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.
1. A memory controller, comprising:
a memory interface queue having an output coupled to a memory channel adapted for coupling to at least one dynamic random access memory (DRAM);
an arbiter coupled to the memory interface queue for selecting memory commands and placing them in the memory interface queue to be transmitted over the memory channel;
a refresh control circuit coupled to the arbiter and operable to monitor an activate counter which maintains a count related to a number of activate commands sent over the memory channel to a memory region, and in response to the activate counter being above a designated threshold, signal the arbiter that a refresh command should be sent to the memory region; and
an activate counter adjustment circuit coupled to the activate counter and operable to respond to a designated condition by adjusting a value of the activate counter by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.
2. The memory controller of claim 1 , wherein:
the designated condition is that one of a refresh command and a refresh management command is sent to the memory region; and
the total number is produced by reducing the first fixed number by the second varying number; and
adjusting the value of the activate counter comprises decrementing the activate counter by the total number.
3. The memory controller of claim 2 , wherein the second varying number is selected from a numerical range comprising “1” to no greater than the first fixed number.
4. The memory controller of claim 2 , wherein the second varying number is selected from a numerical range comprising “1” to a value less than the first fixed number and selected to bias random variation of the activate counter adjustment toward a larger, and therefore less frequent, decrement.
5. The memory controller of claim 1 , wherein the first fixed number is a Rolling Accumulated Activate (RAA) decrement value provided in a control register for the memory controller.
6. The memory controller of claim 1 , wherein:
the designated condition is that an activate command is sent to the memory region; and
the first fixed number is “1”, the second varying number is selected from a set of values including at least “0” and “1”, and the total number is the first fixed number plus the second varying number; and
adjusting the value of the activate counter comprises adding the total number to a previous value of the activate counter.
7. The memory controller of claim 1 , further comprising a pseudo-random number generator (PRNG) coupled to the activate counter adjustment circuit for selecting the second varying number.
8. A method, comprising:
selectively placing memory commands in a memory interface queue and transmitting the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM);
maintaining an activate counter related to a number of activate commands sent over the memory channel to a memory region of the DRAM;
in response to the activate counter being at or above a designated threshold, signaling an arbiter that a refresh command should be sent to the memory region; and
in response to a designated condition, adjusting a value of the activate counter by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.
9. The method of claim 8 , wherein:
the designated condition is that one of a refresh command and a refresh management command is sent to the memory region; and
the total number is produced by reducing the first fixed number by the second varying number; and
adjusting the value of the activate counter comprises decrementing the activate counter by the total number.
10. The method of claim 9 , wherein the second varying number is selected from a numerical range comprising “1” to no greater than the first fixed number.
11. The method of claim 9 , wherein the second varying number is selected from a numerical range comprising “1” to a value less than the first fixed number and selected to bias random variation of the activate counter adjustment toward a larger, and therefore less frequent, decrement.
12. The method of claim 8 , wherein the first fixed number is a Rolling Accumulated ACT (RAA) decrement value provided in a control register.
13. The method of claim 8 , wherein:
the designated condition is that an activate command is sent to the memory region; and
the first fixed number is “1”, the second varying number is selected from a set of values including at least “0” and “1”, and the total number is the first fixed number plus the second varying number; and
adjusting the value of the activate counter comprises adding the total number to the value of the activate counter.
14. A data processing system, comprising:
a data processor;
a data fabric coupled to the data processor; and
a memory controller coupled to the data fabric for fulfilling memory requests from the data processor, the memory controller comprising:
a memory interface queue having an output coupled to a memory channel adapted for coupling to at least one dynamic random access memory (DRAM);
an arbiter coupled to the memory interface queue for selecting memory commands and placing them in the memory interface queue to be transmitted over the memory channel;
a refresh control circuit coupled to the arbiter and operable to monitor an activate counter which maintains a count related to a number of activate commands sent over the memory channel to a memory region, and in response to the activate counter being above a designated threshold, signal the arbiter that a refresh command should be sent to the memory region; and
an activate counter adjustment circuit coupled to the activate counter and operable to respond to a designated condition by adjusting a value of the activate counter by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.
15. The data processing system of claim 14 , wherein:
the designated condition is that one of a refresh command and a refresh management command is sent to the memory region; and
the total number is produced by reducing the first fixed number by the second varying number; and
adjusting the value of the activate counter comprises decrementing the activate counter by the total number.
16. The data processing system of claim 15 , wherein the second varying number is selected from a numerical range comprising “1” to no greater than the first fixed number.
17. The data processing system of claim 15 , wherein the second varying number is selected from a numerical range comprising “1” to a value less than the first fixed number and selected to bias random variation of the activate counter adjustment toward a larger, and therefore less frequent, decrement.
18. The data processing system of claim 14 , wherein the first fixed number is a Rolling Accumulated ACT (RAA) decrement value provided in a control register for the memory controller.
19. The data processing system of claim 14 , wherein:
the designated condition is that an activate command is sent to the memory region; and
the first fixed number is “1”, the second varying number is selected from a set of values including at least “0” and “1”, and the total number is the first fixed number plus the second varying number; and
adjusting the value of the activate counter comprises adding the total number to a previous value of the activate counter.
20. The data processing system of claim 14 , further comprising a pseudo-random number generator (PRNG) coupled to the activate counter adjustment circuit for selecting the second varying number.