Rapid single flux quantum pulse multiplier

1. The method of generating an output signal based on a single flux quantum (SFQ) pulse, the method comprising:

receiving the SFQ pulse;

splitting the SFQ pulse into a first path and a second path;

storing the split SFQ pulse of the second path in a latch;

providing a second splitting of the split SFQ pulse of the first path to provide a first output signal and a second output signal of the first path;

delaying the second output signal by a delay Josephson transmission line (JTL);

providing an output of the delay JTL as a clock input to the latch; and

recombining the first output of the first path with an output of the latch to provide an output signal.

2. The method of claim 1 , wherein:

the latch is a D-latch; and

the split SFQ pulse of the second path is stored in the latch as a circulating supercurrent.

3. The method of claim 1 , wherein the recombination of the first output of the first path with an output of the latch is by way of a confluence buffer.

4. The method of claim 1 , further comprising:

passing the split SFQ pulse through one or more Josephson transmission lines (JTLs) to a first splitter; and

passing an output of the latch through one or more JTLs to a confluence buffer.

5. The method of claim 1 , wherein the delay JTL comprises a series chain of n JTL stages, each having a nominal current bias resulting in a delay Δt, wherein Δt=n×Δt′, where Δt′ is a temporal pulse delay per JTL stage.

6. The method of claim 1 , wherein the delay JTL comprises a series chain of n JTL stages and is configured to receive a controllable global bias current such that a resulting delay Δt=n×Δt′(I b ) where Δt′(I b ) is a temporal pulse delay per JTL stage as a function of a bias current I b .

7. The method of claim 1 , wherein the delay JTL comprises a series chain of n JTL stages, each stage having its own independent bias current such that a resulting delay Δt=Σ i n Δt i (I b,i ), where Δtt(I b,i ) is a delay of the i th stage as a function of its bias current I b .

8. The method of claim 1 , further comprising providing an exponential frequency multiplication of the received SFQ pulse train by setting a delay of each sequential delay JTL stage to be Δt/2 n , where n is a number of the delay JTL stage in a linear chain of N stages of the method, such that an output train of pulses of the output signal have a pulse-to-pulse spacing of Δt/2 N .

9. The method of claim 1 , further comprising providing an odd order of frequency multiplication of the received SFQ pulse by providing at least two cascaded stages of the method, wherein a delay between an upper track and a lower track of pulses for a first doubler stage is 2Δt/3 and a delay between an upper track and a lower track of pulses for a second doubler stage is Δt/3.

10. The circuit, comprising:

a first splitter having a first output and a second output and configured to receive a single flux quantum (SFQ) pulse;

a second splitter coupled to the first output of the first splitter;

a delay Josephson transmission line (JTL) coupled to a second output of the second splitter;

a latch having a data input coupled to the second output of the first splitter and a clock input coupled to an output of the delay JTL; and

a recombination circuit configured to receive the second output of the second splitter and an output of the latch to provide a recombined output.

11. The circuit of claim 10 , wherein:

the latch is a D-latch; and

the latch is configured to store the split SFQ pulse of the second path as a circulating supercurrent.

12. The circuit of claim 10 , wherein the recombination circuit is a confluence buffer.

13. The circuit of claim 10 , further comprising one or more JTLs coupled between the first splitter and the second splitter.

14. The circuit of claim 10 , further comprising one or more JTLs coupled between the latch and the recombination circuit.

15. The circuit of claim 10 , wherein the delay JTL comprises a series chain of n JTL stages, each having a nominal current bias resulting in a delay Δt, wherein Δt=n×Δt′, where Δt′ is a temporal pulse delay per JTL stage.

16. The circuit of claim 10 , wherein the delay JTL comprises a series chain of n JTL stages and is configured to receive a controllable global bias current such that a resulting delay Δt=n×Δt′(I b ) where Δt′(I b ) is the temporal pulse delay per JTL stage as a function of a bias current I b .

17. The circuit of claim 10 , wherein the delay JTL comprises a series chain of n JTL stages, each stage having its own independent bias current such that a resulting delay is Δt=Σ i n Δt i (I b,i ), wherein Δt i (I b,i ) is a delay of the i th stage as a function of its bias current I b .

18. The circuit of claim 10 , wherein a delay of the delay JTL is set to be Δt/2 n , where n is a pulse doubler stage in a chain of N serially connected pulse doublers resulting in an output train of pulses of the output signal having a pulse-to-pulse spacing of Δt/2 N thereby facilitating an even number of frequency multiplication of the received SFQ pulse.

19. The circuit of claim 10 , wherein the circuit is part of a cascade of at least two stages configured to have a delay of each delay JTL to be 2Δt/3, thereby facilitating an odd number of frequency multiplication of the received SFQ pulse.