IP Library › Granted Patent US 11,600,698
Granted Patent B2
US 11,600,698 · App. 17/118,888 · Granted Mar 7, 2023

Semiconductor devices

Inventors: Namkyu Edward Cho (Seongnam-si, KR); Seung Soo Hong (Incheon, KR); Geum Jung Seong (Seoul, KR); Seung Hun Lee (Hwaseong-si, KR); Jeong Yun Lee (Hwaseong-si, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01L29/0847H01L21/02532H01L21/02576H01L21/02579H01L21/02636H01L21/30604H01L21/31111H01L21/823814H01L21/823821H01L21/823828H01L27/0207H01L27/0924H01L27/1104H01L29/0649H01L29/0869H01L29/165H01L29/7848
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Quick Facts
Patent No.
US 11,600,698
App. No.
17/118,888
Granted
Mar 7, 2023
Kind
B2
Abstract

A semiconductor device includes fin patterns on a substrate, at least one gate electrode intersecting the fin patterns, source/drain regions on upper surfaces of the fin patterns, and at least one blocking layer on a sidewall of a first fin pattern of the fin patterns, the at least one blocking layer extending above an upper surface of the first fin pattern of the fin patterns, wherein a first source/drain region of the source/drain regions that is on the upper surface of the first fin pattern has an asymmetric shape and is in direct contact with the at least one blocking layer.

Claims (77)

1. A semiconductor device, comprising:

a substrate;

a first fin on the substrate;

a second fin on the substrate;

a third fin on the substrate;

a fourth fin on the substrate;

a first isolation on the substrate, the first isolation being between the first fin and the second fin;

a second isolation on the substrate, the second isolation being between the second fin and the third fin;

a third isolation on the substrate, the third isolation being between the third fin and the fourth fin;

a gate on the first fin, the second fin, the third fin, the fourth fin, the first isolation, the second isolation, and the third isolation;

a first epitaxial source/drain on the first fin;

a second epitaxial source/drain on the second fin;

a third epitaxial source/drain on the third fin;

a fourth epitaxial source/drain on the fourth fin;

a first blocking pattern on the first isolation, the first blocking pattern contacting and extending along a side surface of each of the second fin and the second epitaxial source/drain; and

a second blocking pattern on the third isolation, the second blocking pattern contacting and extending along a side surface of each of the third fin and the third epitaxial source/drain,

wherein the second epitaxial source/drain and the third epitaxial source/drain are merged and are spaced apart from each of the first epitaxial source/drain and the fourth epitaxial source/drain, neither of the second epitaxial source/drain and the third epitaxial source/drain extending laterally beyond the first blocking pattern and the second blocking pattern, respectively, when extending laterally in a direction toward the first and second blocking patterns, respectively,

wherein a width of the second isolation is less than a width of the first isolation and less than a width of the third isolation, and

wherein a height of the first blocking pattern is substantially the same as a height of the second blocking pattern.

2. The semiconductor device of claim 1 , wherein the first blocking pattern contacts the second fin, and the second blocking pattern contacts the third fin.

3. The semiconductor device of claim 1 , wherein the first blocking pattern and the second blocking pattern are substantially symmetrically disposed with respect to the merged second and third epitaxial source/drains, and are substantially symmetrically shaped with respect to the merged second and third epitaxial source/drains.

4. The semiconductor device of claim 1 , wherein each of the second epitaxial source/drain and the third epitaxial source/drain has a lateral vertex at its maximum width, the maximum width being measured along a direction parallel to the substrate, and an upper end of each of the first blocking pattern and the second blocking pattern is at a substantially same height level as the lateral vertex of the second epitaxial source/drain and the third epitaxial source/drain, respectively.

5. The semiconductor device of claim 1 , wherein the second epitaxial source/drain and the third epitaxial source/drain are substantially symmetrically disposed and shaped with respect to a vertical central line of the merged second and third epitaxial source/drains.

6. The semiconductor device of claim 1 , wherein:

the second epitaxial source/drain is asymmetrically shaped with respect to a vertical central line of the second epitaxial source/drain, and

the third epitaxial source/drain is asymmetrically shaped with respect to a vertical central line of the third epitaxial source/drain.

7. The semiconductor device of claim 1 , further comprising a spacer on the second isolation, the spacer contacting the second fin and the third fin.

8. The semiconductor device of claim 1 , further comprising a gate isolation pattern separating the gate into a first portion and a second portion.

9. A semiconductor device, comprising:

a substrate;

a first fin on the substrate;

a second fin on the substrate;

a third fin on the substrate;

a fourth fin on the substrate;

a first isolation on the substrate, the first isolation being between the first fin and the second fin;

a second isolation on the substrate, the second isolation being between the second fin and the third fin;

a third isolation on the substrate, the third isolation being between the third fin and the fourth fin;

a gate on the first fin, the second fin, the third fin, the fourth fin, the first isolation, the second isolation, and the third isolation;

a first epitaxial source/drain on the first fin;

a second epitaxial source/drain on the second fin;

a third epitaxial source/drain on the third fin;

a fourth epitaxial source/drain on the fourth fin;

a first blocking pattern on the first isolation, the first blocking pattern contacting and extending along a side surface of each of the second fin and the second epitaxial source/drain; and

a second blocking pattern on the third isolation, the second blocking pattern contacting and extending along a side surface of each of the third fin and the third epitaxial source/drain,

wherein the second epitaxial source/drain and the third epitaxial source/drain are merged and are spaced apart from each of the first epitaxial source/drain and the fourth epitaxial source/drain, neither of the second epitaxial source/drain and the third epitaxial source/drain extending laterally beyond the first blocking pattern and the second blocking pattern, respectively, when extending laterally in a direction toward the first and second blocking patterns, respectively,

wherein a width of the second isolation is less than a width of the first isolation and less than a width of the third isolation, and

wherein a top portion of the first blocking pattern is at a higher level than a top portion of the second blocking pattern.

10. The semiconductor device of claim 9 , wherein the first blocking pattern contacts the second fin, and the second blocking pattern contacts the third fin.

11. The semiconductor device of claim 9 , wherein the second epitaxial source/drain is shaped differently from the third epitaxial source/drain.

12. The semiconductor device of claim 9 , wherein a maximum width of the second epitaxial source/drain is less than a maximum width of the third epitaxial source/drain, the maximum width of each of the second epitaxial source/drain and the third epitaxial source/drain being measured along a direction parallel to the substrate.

13. The semiconductor device of claim 9 , wherein each of the first blocking pattern and the second blocking pattern includes SiO, SiN, SiCN, SiOC, SiON or SiOCN.

14. The semiconductor device of claim 9 , further comprising:

a spacer on the second isolation and contacting the second fin and the third fin; and

a gate isolation pattern separating the gate into a first portion and a second portion.

15. A semiconductor device, comprising:

a substrate;

a first fin on the substrate;

a second fin on the substrate;

a third fin on the substrate;

a fourth fin on the substrate;

a first isolation on the substrate, the first isolation being between the first fin and the second fin;

a second isolation on the substrate, the second isolation being between the second fin and the third fin;

a third isolation on the substrate, the third isolation being between the third fin and the fourth fin;

a gate on the first fin, the second fin, the third fin, the fourth fin, the first isolation, the second isolation, and the third isolation;

a first epitaxial source/drain on the first fin;

a second epitaxial source/drain on the second fin;

a third epitaxial source/drain on the third fin;

a fourth epitaxial source/drain on the fourth fin; and

a blocking pattern on the first isolation, the blocking pattern contacting and extending along a side surface of each of the first fin and the first epitaxial source/drain, and the first epitaxial source/drain not extending laterally beyond the blocking pattern when extending laterally in a direction toward the blocking pattern,

wherein the second epitaxial source/drain and the third epitaxial source/drain are merged and are spaced apart from each of the first epitaxial source/drain and the fourth epitaxial source/drain,

wherein a width of the second isolation is less than a width of the first isolation and less than a width of the third isolation, and

wherein a top portion of the fourth epitaxial source/drain is at a higher level than a top portion of the first epitaxial source/drain.

16. The semiconductor device of claim 15 , wherein the blocking pattern contacts the first fin, the blocking pattern being a single blocking pattern contacting the first fin and the first epitaxial source/drain, and the blocking pattern being between the first epitaxial source/drain and the second epitaxial source/drain.

17. The semiconductor device of claim 15 , wherein the width of the first isolation is less than the width of the third isolation.

18. The semiconductor device of claim 15 , wherein a height of the first epitaxial source/drain is less than a height of the fourth epitaxial source/drain.

19. The semiconductor device of claim 15 , wherein the side surface of the first epitaxial source/drain contacted by the blocking pattern is not merged to another epitaxial source/drain.

20. The semiconductor device of claim 15 , further comprising a spacer on the second isolation and contacting the second fin and the third fin.

Priority Claims (1)
KR 10-2018-0029753 · Mar 14, 2018 · national
Continuity (2)
Continuation 15992401 · May 30, 2018
Related Publication 20210098577A1 · Apr 1, 2021