IP Library Granted Patent US 11,404,312
Granted Patent B2
US 11,404,312 · App. 17/120,696 · Granted Aug 2, 2022

Contact plug with impurity variation

Inventors: Chung-Chiang Wu (Taichung, TW); Hsueh Wen Tsau (Zhunan Township, TW); Chia-Ching Lee (New Taipei, TW); Cheng-Lung Hung (Hsinchu, TW); Ching-Hwanq Su (Tainan, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L21/76871H01L21/7684H01L21/76805H01L21/76843H01L21/76862H01L21/76889H01L21/76895H01L23/535H01L23/53266H01L29/66795H01L29/7851
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Quick Facts
Patent No.
US 11,404,312
App. No.
17/120,696
Granted
Aug 2, 2022
Kind
B2
Abstract

A method includes forming an opening in a dielectric layer, depositing a seed layer in the opening, wherein first portions of the seed layer have a first concentration of impurities, exposing the first portions of the seed layer to a plasma, wherein after exposure to the plasma the first portions have a second concentration of impurities that is less than the first concentration of impurities, and filling the opening with a conductive material to form a conductive feature. In an embodiment, the seed layer includes tungsten, and the conductive material includes tungsten. In an embodiment, the impurities include boron.

Claims (31)

1. A semiconductor device comprising:

a dielectric layer; and

a contact plug in the dielectric layer, the contact plug comprising:

a conductive material; and

a conductive layer along sidewalls of the conductive material, a first portion of the conductive layer proximal a first end of the conductive material comprising a first concentration of a first impurity, a second portion of the conductive layer proximal a second end of the conductive material comprising a second concentration of the first impurity, wherein the first end of the conductive material is opposite the second end of the conductive material, and wherein the second concentration of the first impurity is less than the first concentration of the first impurity, wherein the first impurity comprises boron.

2. The semiconductor device of claim 1 , wherein the contact plug is a source/drain contact of a FinFET device.

3. The semiconductor device of claim 1 , wherein the conductive layer is a nucleation layer.

4. The semiconductor device of claim 1 , wherein a concentration of the impurities is higher along opposing surfaces of the contact plug than a middle region interposed between the opposing surfaces of the contact plug.

5. The semiconductor device of claim 1 , wherein the conductive layer comprises tungsten.

6. The semiconductor device of claim 1 , further comprising a barrier layer interposed between the conductive layer and the dielectric layer.

7. The semiconductor device of claim 1 , wherein an upper surface of the conductive layer is recessed from an upper surface of the conductive material.

8. The semiconductor device of claim 7 , wherein the upper surface of the conductive layer is recessed from the upper surface of the conductive material less than 2 nm.

9. A semiconductor device comprising:

a conductive feature;

a first dielectric layer over the conductive feature; and

a contact plug extending through the first dielectric layer to the conductive feature, wherein the contact plug comprises a first conductive layer and a second conductive layer over the first conductive layer, wherein an upper surface of the first conductive layer is recessed from an upper surface of the first conductive layer, wherein the first conductive layer comprises impurities, wherein the first conductive layer has a first concentration of impurities adjacent a lower sidewall of the first dielectric layer and a second concentration of impurities adjacent an upper sidewall of the first dielectric layer, wherein the first concentration is greater than the second concentration.

10. The semiconductor device of claim 9 , wherein the upper surface of the first conductive layer is recessed from an upper surface of the first dielectric layer.

11. The semiconductor device of claim 10 , wherein the upper surface of the first conductive layer is recessed from the upper surface of the first conductive layer less than 2 nm.

12. The semiconductor device of claim 9 , wherein the second concentration is between 5% and 20% less than the first concentration.

13. The semiconductor device of claim 9 , wherein the first conductive layer comprises a first tungsten layer, and wherein the second conductive layer comprises a second tungsten layer.

14. The semiconductor device of claim 9 , wherein the impurities comprise boron.

15. The semiconductor device of claim 9 , wherein the first concentration of impurities is a first concentration of boron or oxygen impurities, wherein the second concentration of impurities is a second concentration of boron or oxygen impurities.

16. A semiconductor device comprising:

a conductive feature;

a first dielectric layer over the conductive feature, the first dielectric layer having an opening extending from an upper surface of the first dielectric layer to the conductive feature;

a barrier layer extending along a sidewall of the opening in the first dielectric layer;

a first conductive layer over the barrier layer, the first conductive layer having a first concentration of boron impurities at a first point on the sidewall of the opening in the first dielectric layer, the first conductive layer having a second concentration of boron impurities at a second point on the sidewall of the opening in the first dielectric layer, the first point being higher than the second point, the first concentration being less than the second concentration; and

a second conductive layer over the first conductive layer.

17. The semiconductor device of claim 16 , wherein an upper surface of the first conductive layer is recessed from the upper surface of the first dielectric layer.

18. The semiconductor device of claim 17 , wherein the upper surface of the first conductive layer is recessed from the upper surface of the first dielectric layer less than 2 nm.

19. The semiconductor device of claim 18 , wherein the upper surface of the first conductive layer is recessed from an upper surface of the second conductive layer.

Continuity (2)
Division 15967497 · Apr 30, 2018
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