IP Library Granted Patent US 11,575,896
Granted Patent B2
US 11,575,896 · App. 17/120,995 · Granted Feb 7, 2023

Encoder, decoder, encoding method, and decoding method

Inventors: Hideo Saitou (Ishikawa, JP); Masato Ohkawa (Toyama, JP); Kiyofumi Abe (Osaka, JP); Takahiro Nishi (Nara, JP); Tadamasa Toma (Osaka, JP); Yusuke Kato (Osaka, JP)
Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
H04N19/124H04N19/136H04N19/176H04N19/18H04N19/182
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Quick Facts
Patent No.
US 11,575,896
App. No.
17/120,995
Granted
Feb 7, 2023
Kind
B2
Abstract

An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: generates (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block; and quantizes the transform coefficients included in the current block using at least one of the first quantization matrix or the second quantization matrix, in accordance with a size of the current block.

Claims (66)

1. An encoder comprising:

circuitry; and

memory coupled to the circuitry, wherein

the circuitry, in operation:

generates (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block;

when the size of the current block is larger than or equal to a first size, quantizes the transform coefficients included in the current block using the first quantization matrix and the second quantization matrix; and

when the size of the current block is smaller than the first size, quantizes the transform coefficients included in the current block using only the first quantization matrix.

2. The encoder according to claim 1 , wherein

the first size is 64 pixels×64 pixels.

3. An encoder comprising:

circuitry; and

memory coupled to the circuitry, wherein

the circuitry, in operation:

generates (i) a first quantization matrix for transform coefficients included in a current block to be processed, (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block, and (iii) a third quantization matrix for a direct current (DC) component of the current block;

when the size of the current block is at least a first size, quantizes the transform coefficients included in the current block using the first quantization matrix, the second quantization matrix, and the third quantization matrix;

when the size of the current block is at most a second size smaller than the first size, quantizes the transform coefficients included in the current block using the first quantization matrix; and

when the size of the current block is larger than the second size and smaller than the first size, quantizes the transform coefficients included in the current block using the second quantization matrix.

4. The encoder according to claim 3 , wherein

the first size is 64 pixels×64 pixels,

the second size is 8 pixels×8 pixels, and

the third quantization matrix is a quantization matrix having a size of one coefficient for the DC component.

5. The encoder according to claim 1 , wherein

the circuitry:

generates the first quantization matrix using matrix elements corresponding to the transform coefficients included in the current block; and

generates the second quantization matrix using matrix elements corresponding to transform coefficients in a predetermined range in the low frequency domain.

6. The encoder according to claim 5 , wherein

the circuitry generates a quantization matrix for each of four regions using a corresponding one of four matrix elements, the four regions being obtained by dividing the low frequency domain in the current block into four, the four matrix elements corresponding to the transform coefficients in the predetermined range.

7. The encoder according to claim 5 , wherein

the circuitry (i) generates a quantization matrix for each of three regions of an upper left region, an upper right region, and a lower left region among four regions using a corresponding one of three matrix elements, the four regions being obtained by dividing the low frequency domain in the current block into four, the three matrix elements corresponding to the transform coefficients in the predetermined range, and (ii) generates a quantization matrix for a lower right region among the four regions using matrix elements corresponding to the lower right region among matrix elements included in the first quantization matrix.

8. A decoder comprising:

circuitry; and

memory coupled to the circuitry, wherein

the circuitry, in operation:

generates (i) a first quantization matrix for quantized coefficients included in a current block to be processed and (ii) a second quantization matrix for quantized coefficients included in a low frequency domain among the quantized coefficients included in the current block;

when the size of the current block is larger than or equal to a first size, inverse quantizes the quantized coefficients included in the current block using the first quantization matrix and the second quantization matrix; and

when the size of the current block is smaller than the first size, inverse quantizes the quantized coefficients included in the current block using only the first quantization matrix.

9. The decoder according to claim 8 , wherein

the first size is 64 pixels×64 pixels.

10. A decoder comprising:

circuitry; and

memory coupled to the circuitry, wherein

the circuitry, in operation:

generates (i) a first quantization matrix for quantized coefficients included in a current block to be processed, (ii) a second quantization matrix for quantized coefficients included in a low frequency domain among the quantized coefficients included in the current block, and (iii) a third quantization matrix for a direct current (DC) component of the current block;

when the size of the current block is at least a first size, inverse quantizes the quantized coefficients included in the current block using the first quantization matrix, the second quantization matrix, and the third quantization matrix;

when the size of the current block is at most a second size smaller than the first size, inverse quantizes the quantized coefficients included in the current block using the first quantization matrix; and

when the size of the current block is larger than the second size and smaller than the first size, inverse quantizes the quantized coefficients included in the current block using the second quantization matrix.

11. The decoder according to claim 10 , wherein

the first size is 64 pixels×64 pixels,

the second size is 8 pixels×8 pixels, and

the third quantization matrix is a quantization matrix having a size of one coefficient for the DC component.

12. The decoder according to claim 8 , wherein

the circuitry:

generates the first quantization matrix using matrix elements corresponding to the quantized coefficients included in the current block; and

generates the second quantization matrix using matrix elements corresponding to quantized coefficients in a predetermined range in the low frequency domain.

13. The decoder according to claim 12 , wherein

the circuitry generates a quantization matrix for each of four regions using a corresponding one of four matrix elements, the four regions being obtained by dividing the low frequency domain in the current block into four, the four matrix elements corresponding to the quantized coefficients in the predetermined range.

14. The decoder according to claim 12 , wherein

the circuitry (i) generates a quantization matrix for each of three regions of an upper left region, an upper right region, and a lower left region among four regions using a corresponding one of three matrix elements, the four regions being obtained by dividing the low frequency domain in the current block into four, the three matrix elements corresponding to the quantized coefficients in the predetermined range, and (ii) generates a quantization matrix for a lower right region among the four regions using matrix elements corresponding to the lower right region among matrix elements included in the first quantization matrix.

15. An encoding method comprising:

generating (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block;

when the size of the current block is larger than or equal to a first size, quantizing the transform coefficients included in the current block using the first quantization matrix and the second quantization matrix; and

when the size of the current block is smaller than the first size, quantizing the transform coefficients included in the current block using only the first quantization matrix.

16. A decoding method comprising:

generating (i) a first quantization matrix for quantized coefficients included in a current block to be processed and (ii) a second quantization matrix for quantized coefficients included in a low frequency domain among the quantized coefficients included in the current block;

when the size of the current block is larger than or equal to a first size, inverse quantizing the quantized coefficients included in the current block using the first quantization matrix and the second quantization matrix; and

when the size of the current block is smaller than the first size, inverse quantizing the quantized coefficients included in the current block using only the first quantization matrix.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 5, 2021
From: SAITOU, HIDEO; OHKAWA, MASATO; ABE, KIYOFUMI; NISHI, TAKAHIRO; TOMA, TADAMASA; KATO, YUSUKE
To: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
Reel/Frame 056754/0677 →
Continuity (2)
Provisional Application 62948431 · Dec 16, 2019
Related Publication 20210289205A1 · Sep 16, 2021