Apparatus for non-volatile random access memory stacks
A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
1. A memory structure, comprising:
a NAND block comprising a plurality of oxide layers stacked in a vertical direction, the plurality of oxide layers forming a staircase structure at a first edge of the NAND block;
a plurality of vias disposed on the staircase structure of the NAND block, two or more of the plurality of vias terminating along a same plane;
a plurality of first bonding interconnects electrically connected with the plurality of vias;
a plurality of bitlines extending across the NAND block; and
a plurality of second bonding interconnects electrically connected with the bitlines, wherein the bitlines are disposed between the second bonding interconnects and the oxide layers in the vertical direction.
2. The memory structure of claim 1 , wherein the plurality of first bonding interconnects are substantially aligned in a same plane with the plurality of second bonding interconnects.
3. The memory structure of claim 2 , wherein the plurality of first bonding interconnects and the plurality of second bonding interconnects are embedded in a dielectric.
4. The memory structure of claim 1 , wherein the plurality of second bonding interconnects are spaced at a pitch at or greater than a wordline contact pitch.
5. The memory structure of claim 1 , further comprising a logic wafer, wherein the logic wafer is face-to-face bonded with the plurality of vias and the bitlines through the first and second bonding interconnects.
6. The memory structure of claim 5 , wherein the logic wafer includes a plurality of bonding interconnects on a bonding surface of the logic wafer.
7. The memory structure of claim 6 , wherein the plurality of bonding interconnects of the logic wafer are bonded to the plurality of vias and the bitlines using a non-adhesive direct bonding technique or a non-adhesive hybrid bonding technique.
8. The memory structure of claim 1 , further comprising at least one slit formed in the plurality of oxide layers, the at least one slit separating a first wordline structure from a second wordline structure.
9. The memory structure of claim 8 , wherein the bitlines extend across the at least one slit.
10. The memory structure of claim 1 , wherein the plurality of first bonding interconnects are disposed on the plurality of vias.
11. The memory structure of claim 1 , wherein the plurality of second bonding interconnects are disposed along the bitlines.
12. A stacked memory device, comprising:
at least one first stack layer; and
at least one second stack layer;
wherein each of the at least one first stack layer and the at least one second stack layer comprises a stack of layers stacked in a vertical direction and further comprises:
a NAND block comprising a plurality of oxide layers, the plurality of oxide layers forming a staircase structure at a first edge of the NAND block;
a first plurality of vias disposed on the staircase structure of the NAND block;
a second plurality of vias disposed at the first edge of the NAND block;
a plurality of first bonding interconnects electrically connected to the second plurality of vias;
a plurality of bitlines extending across the NAND block; and
a plurality of second bonding interconnects electrically connected to the bitlines, wherein the bitlines are disposed between the second bonding interconnects and the stack of layers in the vertical direction.
13. The stacked memory device of claim 12 , wherein the plurality of first bonding interconnects are in a same plane with the plurality of second bonding interconnects or embedded in a dielectric.
14. The stacked memory device of claim 13 , wherein the plurality of first bonding interconnects and the plurality of second bonding interconnects are all in one plane embedded in the dielectric.
15. The stacked memory device of claim 12 , further comprising at least one slit formed in the stack of layers, the at least one slit separating a first wordline structure from a second wordline structure.
16. The stacked memory device of claim 15 , wherein the bitlines extend across the at least one slit.
17. The stacked memory device of claim 16 , further comprising a plurality of third vias disposed within the at least one slit.
18. The stacked memory device of claim 17 , further comprising a plurality of fourth vias disposed outside the first and second stack layers.
19. The stacked memory device of claim 17 , wherein the plurality of second bonding interconnects are disposed along the bitlines and are substantially aligned with the third plurality of vias.
20. The stacked memory device of claim 12 , wherein the plurality of second bonding interconnects are spaced at a wordline contact pitch.
21. The stacked memory device of claim 20 , wherein each of the at least one first stack layer and the at least one second stack layer further comprises a bitline redistribution layer disposed on an opposing side of the NAND block from the bitlines.
22. The stacked memory device of claim 12 , wherein each of the at least one first stack layer and the at least one second stack layer further comprises a silicon layer.
23. The stacked memory device of claim 22 , wherein the silicon layer comprises logic for one or more operations within the at least one first stack layer and the at least one second stack layer.
24. The stacked memory device of claim 23 , wherein the operations comprise switching operations.
25. The stacked memory device of claim 23 , further comprising a shift register.
26. The stacked memory device of claim 12 , wherein each of the at least one first stack layer and the at least one second stack layer includes an amount of remaining silicon.
27. The stacked memory device of claim 26 , wherein the amount of remaining silicon is between 0.1 μm to 6 μm thick.
28. The stacked memory device of claim 26 , wherein the amount of remaining silicon is between 6 μm to 20 μm thick.
29. The stacked memory device of claim 12 , wherein each NAND block further comprises logic for addressing at least one of data, wordline selection, serialization of data, or deserialization of data.
30. The stacked memory device of claim 12 , further comprising a third layer, the third layer comprising a logic layer, wherein a silicon substrate has been completely removed from the at least one first stack layer and the at least one second stack layer.
31. The stacked memory device of claim 12 , wherein the at least one first stack layer is direct bonded to the at least one second stack layer.