Contact over active gate structures with tapered gate or trench contact for advanced integrated circuit structure fabrication
Contact over active gate (COAG) structures with a tapered gate or trench contact are described. In an example, an integrated circuit structure includes a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers. A conductive structure is in direct contact with the conductive cap and sidewall spacers on one of the plurality of gate structures or with the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures.
1. An integrated circuit structure, comprising:
a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers, the sidewall spacers on a top surface of and entirely within a footprint of the corresponding individual one of the plurality of gate structures, and the sidewall spacers having an uppermost surface above an uppermost surface of the conductive cap;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers;
an etch stop layer over the plurality of gate structures and over the plurality of conductive trench contact structures;
an interlayer dielectric material over the etch stop layer;
an opening in the interlayer dielectric material and in the etch stop layer, the opening exposing the conductive cap and sidewall spacers on one of the plurality of gate structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive cap and sidewall spacers on the one of the plurality of gate structures.
2. The integrated circuit structure of claim 1 , further comprising a dielectric spacer along sides of the one of the plurality of gate structures, wherein the opening exposes a portion of the dielectric spacer.
3. The integrated circuit structure of claim 1 , further comprising a remnant portion of the etch stop layer between the conductive structure and the conductive cap on the one of the plurality of gate structures.
4. The integrated circuit structure of claim 1 , wherein the conductive structure has an uppermost surface co-planar with an uppermost surface of the interlayer dielectric material.
5. The integrated circuit structure of claim 1 , wherein the etch stop layer comprises aluminum and oxygen, and the sidewall spacers comprise silicon and nitrogen.
6. An integrated circuit structure, comprising:
a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers, the sidewall spacers on a top surface of and entirely within a footprint of the corresponding individual one of the plurality of gate structures, and the sidewall spacers having an uppermost surface above an uppermost surface of the conductive cap;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers;
an etch stop layer over the plurality of gate structures and over the plurality of conductive trench contact structures;
an interlayer dielectric material over the etch stop layer;
an opening in the interlayer dielectric material and in the etch stop layer, the opening exposing the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive cap and sidewall spacers on the one of the conductive trench contact structures.
7. The integrated circuit structure of claim 6 , further comprising a dielectric spacer along sides of the one of the conductive trench contact structures, wherein the opening exposes a portion of the dielectric spacer.
8. The integrated circuit structure of claim 6 , further comprising a remnant portion of the etch stop layer between the conductive structure and the conductive cap spacers on the one of the conductive trench contact structures.
9. The integrated circuit structure of claim 6 , wherein the conductive structure has an uppermost surface co-planar with an uppermost surface of the interlayer dielectric material.
10. The integrated circuit structure of claim 6 , wherein the etch stop layer comprises aluminum and oxygen, and the sidewall spacers comprise silicon and nitrogen.
11. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers, the sidewall spacers on a top surface of and entirely within a footprint of the corresponding individual one of the plurality of gate structures, and the sidewall spacers having an uppermost surface above an uppermost surface of the conductive cap;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers;
an etch stop layer over the plurality of gate structures and over the plurality of conductive trench contact structures;
an interlayer dielectric material over the etch stop layer;
an opening in the interlayer dielectric material and in the etch stop layer, the opening exposing the conductive cap and sidewall spacers on one of the plurality of gate structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive cap and sidewall spacers on the one of the plurality of gate structures.
12. The computing device of claim 11 , further comprising:
a memory coupled to the board.
13. The computing device of claim 11 , further comprising:
a communication chip coupled to the board.
14. The computing device of claim 11 , further comprising:
a camera coupled to the board.
15. The computing device of claim 11 , wherein the component is a packaged integrated circuit die.
16. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a plurality of gate structures above a substrate, wherein individual ones of the plurality gate of structures have thereon a conductive cap between sidewall spacers, the sidewall spacers on a top surface of and entirely within a footprint of the corresponding individual one of the plurality of gate structures, and the sidewall spacers having an uppermost surface above an uppermost surface of the conductive cap;
a plurality of conductive trench contact structures alternating with the plurality of gate structures, wherein individual ones of the plurality of conductive trench contact structures have thereon a conductive cap between sidewall spacers;
an etch stop layer over the plurality of gate structures and over the plurality of conductive trench contact structures;
an interlayer dielectric material over the etch stop layer;
an opening in the interlayer dielectric material and in the etch stop layer, the opening exposing the conductive cap and sidewall spacers on one of the plurality of conductive trench contact structures; and
a conductive structure in the opening, the conductive structure in direct contact with the conductive cap and sidewall spacers on the one of the conductive trench contact structures.
17. The computing device of claim 16 , further comprising:
a memory coupled to the board.
18. The computing device of claim 16 , further comprising:
a communication chip coupled to the board.
19. The computing device of claim 16 , further comprising:
a camera coupled to the board.
20. The computing device of claim 16 , wherein the component is a packaged integrated circuit die.