Semiconductor devices

1. A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least:

one or more semiconductor channels in one or more semiconductor channel regions;

a dielectric;

a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric;

a planarisation layer;

a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via one or more through holes in at least the planarisation layer in one or more through hole regions, and wherein the one or more semiconductor channel regions are at least partly outside the one or more through hole regions; and wherein the device further comprises a retained photoresist mask used at least to form the first conductor pattern.

2. The device according to claim 1 , wherein the one or more through holes are wholly outside the one or more semiconductor channel regions.

3. The device according to claim 1 , wherein:

the stack comprises a third conductor pattern including conductor elements connected in electrical series via the one or more semiconductor channels; and

wherein the one or more through holes are in one or more regions unoccupied by any conductor element of the third conductor pattern.

4. The device according to claim 1 , wherein the second conductor pattern comprises a metal pattern, and the first conductor pattern comprises a conductive metal oxide pattern.

5. The device according to claim 1 , wherein the planarization layer includes no through holes in the one or more semiconductor channel regions.

6. The device according to claim 1 , wherein the retained photoresist mask provides white-light shielding for one or more the semiconductor channels.

7. The device according to claim 1 , wherein the retained photoresist mask comprises a photoresist material and carbon black particles.

8. The device according to claim 1 , wherein the planarization layer comprises a gradual step in border regions between inside and outside the through-hole regions.

9. The device according to claim 1 , wherein the planarization layer includes no other through holes in the one or more semiconductor channel regions.

10. A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least:

a patterned semiconductor layer defining one or more semiconductor channels in one or more semiconductor channel regions;

a patterned dielectric;

a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or more semiconductor channels via the patterned dielectric;

a planarisation layer;

a second conductor pattern defining one or more routing conductors, wherein the second conductor pattern is in contact with the first conductor pattern via one or more through holes in at least the planarisation layer in one or more through hole regions; and

wherein the first conductor pattern is configured not to overlap with a third conductor pattern below the patterned semiconductor layer in the stack, wherein the patterned semiconductor layer and patterned dielectric overlap with parts of the third conductor pattern; wherein the third conductor pattern is formed over parts of a fourth conductor pattern, wherein parts of the fourth conductor pattern uncovered by the third conductor pattern define electrodes connected by the one or more semiconductor channels; and the first conductor pattern overlaps the electrodes, and wherein the device further comprises a retained photoresist mask used at least to form the first conductor pattern.

11. The device according to claim 10 , wherein the first conductor pattern occupies regions unoccupied by the patterned dielectric.

12. The device according to claim 10 , wherein the fourth conductor pattern defines conductor lines, and wherein the third conductor pattern comprises a conductive oxide protecting the conductor lines.

13. A device comprising a stack of layers defining one or more electronic elements, wherein the stack comprises at least:

one or more semiconductor channels in one or more semiconductor channel regions;

a dielectric;

a first conductor pattern defining one or more coupling conductors, wherein the one or more coupling conductors are capacitively coupled to the one or one or more semiconductor channels via the dielectric;

a planarisation layer;

a second conductor pattern defining one or more routing conductors, wherein the one or more routing conductors are in contact with the first conductor pattern via one or more through holes in at least the planarisation layer in one or more through hole regions, wherein the one or more semiconductor channel regions are at least partly outside the through hole regions; and

wherein the routing conductors extend through the semiconductor channel regions; and wherein the device further comprises a retained photoresist mask used at least to form the first conductor pattern.

14. The device according to claim 13 , wherein the retained photoresist mask provides white-light shielding for the one or more semiconductor channels.

15. The device according to claim 13 , wherein the retained photoresist mask comprises a photoresist material and carbon black particles.