Multi-transistor stack bitcell architecture
Various implementations described herein are related to a device having multiple transistors in a single stack arranged as a cross-coupled bitcell latch. Also, the multiple transistors may be disposed in a multi-transistor stack configuration that is formed within a single monolithic semiconductor die. In some implementations, the multiple transistors may be arranged as a bitcell for single-port memory applications.
1. A device comprising:
multiple transistors arranged in a single stack and coupled together to operate as a cross-coupled bitcell latch,
wherein the multiple transistors include N-type transistors and P-type transistors that are sequentially disposed in a P-over-N-over-N-over-P stack configuration that is formed within a single monolithic semiconductor die.
2. The device of claim 1 , wherein:
the multiple transistors include at least four transistors that are disposed in the single stack within the single monolithic semiconductor die, and
the multiple transistors are arranged as a bitcell for single-port memory applications.
3. The device of claim 1 , wherein:
the multiple transistors include a pair of N-type transistors and a pair of P-type transistors that are configured to form two inverter pairs by combining a first N-type transistor from the pair of N-type transistors and a first P-type transistor from the pair of P-type transistors to form a first inverter pair of the two inverter pairs and by combining a second N-type transistor from the pair of N-type transistors and a second P-type transistor from the pair of P-type transistors to form a second inverter pair of the two inverter pairs, and
the two inverter pairs are cross-coupled on sides thereof so as to provide two cross-coupled inverters that are utilized as the cross-coupled bitcell latch.
4. The device of claim 3 , wherein:
the multiple transistors include a first passgate and a second passgate for the bitcell,
the first passgate is coupled between a first bitline and a first inverter of the two cross-coupled inverters, and
the second passgate is coupled between a second bitline and a second inverter of the two cross-coupled inverters.
5. The device of claim 4 , wherein gates of the first passgate and the second passgate are coupled to a wordline for the bitcell.
6. The device of claim 1 , wherein the multiple transistors include field-effect transistors (FET) including P-type FET (PFET) and N-type FET (NFET).
7. The device of claim 1 , wherein the multiple transistors have multiple N-type transistors and multiple P-type transistors, and wherein the multi-transistor stack configuration refers to a P-over-P-over-N-over-N stack configuration.
8. The device of claim 1 , wherein the multiple transistors have multiple N-type transistors and multiple P-type transistors, and wherein the multi-transistor stack configuration refers to an N-over-P-over-P-over-N stack configuration.
9. The device of claim 1 , wherein the multiple transistors have multiple N-type transistors and multiple P-type transistors, and wherein the multi-transistor stack configuration refers to a P-over-N-over-P-over-N stack configuration.
10. A bitcell comprising:
a pair of N-type devices; and
a pair of P-type devices,
wherein the pair of N-type devices and the pair of P-type devices are sequentially formed in a single P-over-N-over-N-over-P stack within a single monolithic semiconductor die.
11. The bitcell of claim 10 , wherein the pair of N-type devices and the pair of P-type devices are cross-coupled on sides thereof so as to provide two cross-coupled inverters that are utilized as a latch for the bitcell.
12. The bitcell of claim 11 , further comprising:
a first passgate and a second passgate,
wherein the first passgate is coupled between a first bitline and a first inverter of the two cross-coupled inverters,
wherein the second passgate is coupled between a second bitline and a second inverter of the two cross-coupled inverters, and
wherein gates of the first passgate and the second passgate are coupled to a wordline for the bitcell.
13. The bitcell of claim 10 , wherein the pair of N-type devices refer to a pair of N-type field-effect transistors (NFET), and wherein the pair of P-type devices refer to a pair of P-type field-effect transistors (PFET).
14. The bitcell of claim 10 , wherein the pair of N-type devices and the pair of P-type devices are disposed in the single stack with a P-over-P-over-N-over-N stack configuration.
15. The bitcell of claim 10 , wherein the pair of N-type devices and the pair of P-type devices are disposed in the single stack with an N-over-P-over-P-over-N stack configuration.
16. The bitcell of claim 10 , wherein the pair of N-type devices and the pair of P-type devices are disposed in the single stack with a P-over-N-over-P-over-N stack configuration.
17. A method comprising:
fabricating multiple transistors that are arranged as a bitcell;
fabricating the multiple devices with a pair of N-type transistors and a pair of P-type transistors sequentially disposed in a single P-over-N-over-N-over-P stack configuration and formed within a single monolithic semiconductor die; and
cross-coupling the pair of N-type transistors with the pair of P-type transistors so as to provide two cross-coupled inverters that are used as a latch for the bitcell.