Metal oxide semiconductor integrated circuit basic unit

1. A metal oxide semiconductor (MOS) integrated circuit basic unit, comprising:

a drain semiconductor region;

a lightly doped drain region;

a channel semiconductor region;

a source semiconductor region;

a source electrode;

a gate electrode;

a gate dielectric layer; and

a drain electrode;

wherein:

the drain semiconductor region is a bottom of the basic unit;

the gate electrode has a ring structure, which surrounds the channel semiconductor region, the source semiconductor region and the lightly doped drain region;

an upper surface of the gate electrode is aligned to an upper surface of the source semiconductor region; and a bottom surface of the gate electrode is lower than an interface of the lightly doped drain region and the drain semiconductor region;

the gate dielectric layer is disposed between the gate electrode and an adjacent functional layer;

the gate dielectric layer provides the isolation between the gate electrode and the source region, and the lightly doped drain region, and the drain semiconductor region; and

the drain semiconductor region is connected to the drain electrode of the basic unit.

2. The circuit of claim 1 , wherein the gate dielectric layer comprises SiO 2 , Si 3 N 4 , HfO 2 , Al 2 O 3 or a combination thereof.

3. The circuit of claim 1 , wherein the source semiconductor region comprises pseudo-crystal SiGe, polycrystalline SiGe, polycrystalline germanium, polycrystalline InP, or polycrystalline HgCdTe; and the channel semiconductor region comprises silicon.

4. The circuit of claim 1 , wherein the channel semiconductor region comprises SiC or GaN, and the source semiconductor region comprises Si or Ge.

5. An inverter, comprising two MOS integrated circuit basic units of claim 1 arranged in parallel; wherein:

the two MOS integrated circuit basic units comprise a first basic unit and a second basic unit; in the first basic unit, the drain semiconductor region is an N + type, the lightly doped drain region is an N − type, the channel semiconductor region is a P type, and the source semiconductor region is an N + type;

in the second basic unit, the drain semiconductor region is a P + type, the lightly doped drain region is a P − type, the channel semiconductor region is an N type, and the source semiconductor region is a P + type;

the first basic unit and the second basic unit share a drain electrode;

the gate electrodes of the first basic unit and the second basic unit are integrated as an entity; and

the gate dielectric layer provides the isolation between the gate electrode and the source semiconductor region, and the lightly doped drain region, and the drain semiconductor region.