Level two first-in-first-out transmission
A hardware state machine connected to a processor, the hardware state machine configured to receive operational codes from the processor; a multiplexer connected to the processor, the hardware state machine and a checksum circuit, the multiplexer configured to receive data from the processor; and a transmit circuit connected to the multiplexer, the transmit circuit configured to receive data from the multiplexer for transmission to a far end device, wherein the hardware state machine is further configured to, responsive receiving one or more operational codes from the processor: cause the checksum circuit to alter a checksum value of a first data packet being transmitted by the transmit circuit; and cause the transmit circuit to preempt transmission of the first data packet and begin transmitting a second data packet once the checksum value so altered has been transmitted from the transmit circuit.
1. A circuit comprising:
a level two transmission circuit configured to couple to a processor to receive a first set of data, a second set of data, and an operational code, wherein the level two transmission circuit includes:
a first-in-first-out (FIFO) buffer;
a set of logic coupled to the FIFO buffer and configured to:
generate a first packet for the first set of data;
generate a second packet for the second set of data; and
based on the operational code, preempt the first packet by:
fragmenting the first packet to produce a first packet fragment and a second packet fragment, wherein the first packet fragment includes a value indicating that the first packet fragment is a fragment; and
provide the second packet for transmission between the first packet fragment and the second packet fragment;
a level one transmission circuit coupled to the level two transmission circuit and configured to couple to a network, wherein the level one transmission circuit is configured to:
receive the first packet fragment, the second packet fragment, and the second packet; and
provide the first packet fragment, the second packet fragment, and the second packet for transmission over the network such that the second packet is transmitted between the first packet fragment and the second packet fragment.
2. The circuit of claim 1 , wherein the value in the first packet fragment indicates a count of fragments that make up in the first packet.
3. The circuit of claim 1 , wherein the value in the first packet fragment further indicates a sequence number of the first packet fragment.
4. The circuit of claim 1 , wherein the first packet fragment includes a cyclical redundancy check value that includes the value that indicates that the first packet fragment is a fragment.
5. The circuit of claim 4 , wherein the set of logic is further configured to, based on the operational code, generate the cyclical redundancy check value of the first packet fragment.
6. The circuit of claim 1 , wherein the set of logic is further configured to, based on the operational code, add a virtual local area tag to the second packet.
7. The circuit of claim 1 , wherein the set of logic is further configured to, based on the operational code, remove a virtual local area tag from the second packet.
8. The circuit of claim 1 , wherein the set of logic is further configured to, based on the operational code, add preamble information to the second packet.
9. The circuit of claim 1 , wherein:
the FIFO buffer of the level two transmission circuit is a first FIFO buffer;
the level one transmission circuit includes a second FIFO buffer; and
the level one transmission circuit is configured to couple to the processor to provide a set of signals based on an amount of data in the second FIFO buffer.
10. The circuit of claim 9 , wherein the set of signals includes at least one of: a FIFO data level signal, an underflow signal, or an overflow signal.
11. The circuit of claim 1 further comprising:
a level one receive circuit configured to couple to the network to receive a third set of data; and
a multiplexer that includes:
a first input coupled to the level one receive circuit to receive the third set of data;
a second input coupled to the level two transmission circuit to receive the second packet, the first packet fragment, and the second packet fragment; and
an output coupled to the level one transmission circuit.
12. A system comprising:
a processor;
a first transmit circuit coupled to the processor and configured to:
receive, from the processor, a first set of data, a second set of data, and an operational code that indicates to preempt the first set of data with the second set of data;
based on the operational code, divide the first set of data among a first packet fragment and a second packet fragment;
generate a second packet for the second set of data; and
provide the first packet fragment, the second packet fragment, and the second packet; and
a second transmit circuit coupled to the first transmit circuit and configured to:
receive the first packet fragment, the second packet fragment, and the second packet;
cause the first packet fragment and the second packet fragment to be transmitted over a network; and
cause the second packet to be transmitted over the network between the first packet fragment and the second packet fragment.
13. The system of claim 12 , wherein the first packet fragment includes a value that indicates that the first packet fragment is a fragment.
14. The system of claim 13 , wherein the value further indicates a sequence number of the first packet fragment.
15. The system of claim 13 , wherein the first packet fragment includes a cyclical redundancy check value that includes the value that indicates that the first packet fragment is a fragment.
16. The system of claim 12 , wherein the first transmit circuit is further configured to, based on the operational code, add a virtual local area tag to the second packet.
17. The system of claim 12 , wherein the first transmit circuit is further configured to, based on the operational code, remove a virtual local area tag from the second packet.
18. The system of claim 12 , wherein:
the second transmit circuit includes a buffer; and
the second transmit circuit configured to provide to the processor a set of signals based on an amount of data in the buffer.
19. The system of claim 18 wherein the set of signals includes at least one of: a buffer data level signal, an underflow signal, or an overflow signal.
20. The system of claim 12 , wherein the first transmit circuit is coupled to the processor by an interface having a width such that the first transmit circuit is configured to receive the first set of data and the second set of data in parallel.