IP Library › Granted Patent US 12,271,249
Granted Patent B2
US 12,271,249 · App. 17/127,417 · Granted Apr 8, 2025

Advanced link power management for displayport

Inventors: Nausheen Ansari (Folsom, CA); Ziv Kabiry (Kfar-Saba, IL); Gal Yedidia (Bitzaron, IL)
Assignee: Intel Corporation
G06F1/3265G06F1/3203G06F1/3287G06T1/20H04N21/44004
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Quick Facts
Patent No.
US 12,271,249
App. No.
17/127,417
Granted
Apr 8, 2025
Kind
B2
Abstract

An apparatus comprising circuitry to buffer video data; and a DisplayPort Transmitter to communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH); and communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states.

Claims (33)

1. An apparatus comprising:

circuitry to buffer video data; and

a DisplayPort Transmitter to:

communicate the video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH);

communicate a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states; and

communicate a plurality of frame indicators to the DisplayPort Receiver after the power down signal is communicated over the Main-Link and prior to communication of a wakeup signal to the DisplayPort Receiver.

2. The apparatus of claim 1 , wherein the at least one intermediate device comprises a plurality of devices to enter respective low power states responsive to receiving the power down signal.

3. The apparatus of claim 1 , wherein an intermediate device of the at least one intermediate device comprises a second DisplayPort Receiver and a second DisplayPort Transmitter.

4. The apparatus of claim 1 , wherein at least one intermediate device comprises one or more of a link training-tunable PHY repeater (LTTPR), a retimer, or a branch device.

5. The apparatus of claim 1 , wherein the power down signal is a first type of power down signal and the DisplayPort Transmitter is further to communicate a second type of power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in different respective low power states.

6. The apparatus of claim 1 , wherein the DisplayPort Transmitter is to transmit valid symbols for an amount of time based on how many intermediate devices are between the DisplayPort Transmitter and the DisplayPort Receiver after communicating the power down signal before turning off the Main-Link.

7. The apparatus of claim 1 , wherein the power down signal is sent using a 128b/132b encoding scheme and the power down signal includes a control data indicator and an additional sequence.

8. The apparatus of claim 1 , wherein the DisplayPort Transmitter is to send a wakeup signal to the at least one intermediate device and the DisplayPort Receiver on the AUX_CH prior to turning the Main-Link back on.

9. The apparatus of claim 1 , wherein the DisplayPort Transmitter is to bring up the Main-Link to transmit a frame indicator of the plurality of frame indicators over the Main-Link to the DisplayPort Receiver and to subsequently turn off the Main-Link until a next frame indicator of the plurality of frame indicators is to be sent to the DisplayPort Receiver, the frame indicator to enable maintenance of synchronization between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the frame indicator does not include active video data.

10. The apparatus of claim 9 , wherein the frame indicator is a blank start.

11. The apparatus of claim 9 , wherein the frame indicator is a secondary data packet.

12. The apparatus of claim 1 , further comprising a graphics processing unit to generate the video data.

13. The apparatus of claim 12 , further comprising a central processing unit in communication with the graphics processing unit.

14. An apparatus comprising:

circuitry to buffer video data; and

a DisplayPort Receiver to:

receive the video data from a DisplayPort Transmitter via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH);

enter a low power state responsive to receiving, from a first intermediate device of the at least one intermediate device, a power down signal sent over the Main-Link by the DisplayPort Transmitter; and

while in the low power state, maintain frame timing synchronization with the DisplayPort Transmitter through a plurality of frame indicators sent by the DisplayPort Transmitter.

15. The apparatus of claim 14 , further comprising a scaler chip including the DisplayPort Receiver.

16. The apparatus of claim 15 , further comprising a display panel to generate light or allow for transmission of light in a plurality of pixels of the display panel.

17. A method comprising:

communicating, by a DisplayPort Transmitter, video data to a DisplayPort Receiver via a virtual channel through at least one intermediate device between the DisplayPort Transmitter and the DisplayPort Receiver, wherein the virtual channel comprises a unidirectional Main-Link and a bidirectional auxiliary channel (AUX_CH);

communicating, by the DisplayPort Transmitter, a power down signal over the Main-Link to the at least one intermediate device and the DisplayPort Receiver in conjunction with turning off the Main-Link to place the at least one intermediate device and the DisplayPort Receiver in respective low power states; and

communicating, by the DisplayPort Transmitter to the DisplayPort Receiver, a plurality of frame indicators to the DisplayPort Receiver after the power down signal is communicated over the Main-Link and prior to communication of a wakeup signal to the DisplayPort Receiver, the plurality of frame indicators to enable the DisplayPort Receiver to maintain frame timing synchronization with the DisplayPort Transmitter.

18. The method of claim 17 , further comprising waiting an amount of time based on how many intermediate devices are between the DisplayPort Transmitter and the DisplayPort Receiver after communicating the power down signal before turning off the Main-Link.

19. The method of claim 17 , further comprising sending, by the DisplayPort Transmitter a wakeup signal to the at least one intermediate device and the DisplayPort Receiver on the Main-Link prior to turning the Main-Link back on.

20. The method of claim 17 , further comprising bringing up the Main-Link to transmit a frame indicator of the plurality of frame indicators over the Main-Link to the DisplayPort Receiver and subsequently turning off the Main-Link until a next frame indicator of the plurality of frame indicators is to be sent to the DisplayPort Receiver, the frame indicator to enable maintenance of synchronization between the DisplayPort Transmitter and the DisplayPort Receiver.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE APPLICATION NUMBER IN THE ASSIGNMENT DOCUMENT PREVIOUSLY RECORDED AT REEL: 054748 FRAME: 0139. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT . Recorded Jan 13, 2022
From: ANSARI, NAUSHEEN; KABIRY, ZIV; YEDIDIA, GAL
To: INTEL CORPORATION
Reel/Frame 058724/0120 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2020
From: ANSARI, NAUSHEEN; KABIRY, ZIV; YEDIDIA, GAL
To: INTEL CORPORATION
Reel/Frame 054748/0139 →
Continuity (1)
Related Publication 20210103327A1 · Apr 8, 2021
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