Microelectronic assemblies
Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
1. A microelectronic assembly, comprising:
a multi-layer structure including multiple layers of dielectric material, wherein the multi-layer structure includes one or more conductive pathways through the dielectric material;
a first die;
a second die, wherein the second die is between the first die and a surface of the multi-layer structure;
a third die, wherein the third die is between the first die and the surface of the multi-layer structure, and
a plane parallel to the surface of the multi-layer structure extends through the second die and the third die; and
a fourth die, wherein the fourth die is coupled to the surface of the multi-layer structure;
wherein:
the first die is bonded directly to the second die by first interconnects,
the first die is bonded directly to the third die by second interconnects, and
the third die includes through-substrate vias (TSVs) through a semiconductor substrate of the third die.
2. The microelectronic assembly of claim 1 , wherein the first interconnects have a pitch between 7 microns and 100 microns.
3. The microelectronic assembly of claim 1 , wherein the second interconnects have a pitch between 7 microns and 100 microns.
4. The microelectronic assembly of claim 1 , wherein the multi-layer structure includes one or more redistribution layers.
5. The microelectronic assembly of claim 1 , further comprising:
a fifth die coupled between the third die and the multi-layer structure, wherein the fifth die is an inactive die.
6. The microelectronic assembly of claim 1 , further comprising:
a mold material between a portion of the first die and the multi-layer structure.
7. The microelectronic assembly of claim 1 , wherein the multi-layer structure includes a package substrate.
8. The microelectronic assembly of claim 1 , wherein a line from the first die to the multi-layer structure, perpendicular to a plane of the surface of the multi-layer structure, passes through the second die.
9. The microelectronic assembly of claim 1 , wherein a line from the first die to the multi-layer structure, perpendicular to a plane of the surface of the multi-layer structure, passes through the third die.
10. The microelectronic assembly of claim 1 , wherein the first interconnects include metal-to-metal interconnects.
11. The microelectronic assembly of claim 1 , wherein the second interconnects include metal-to-metal interconnects.
12. The microelectronic assembly of claim 1 , wherein the first die is bonded to the second die without any dies in between.
13. The microelectronic assembly of claim 1 , wherein the first die is bonded to the third die without any dies in between.
14. The microelectronic assembly of claim 1 , wherein the second die and the third die are spaced apart laterally.
15. A microelectronic assembly, comprising:
a multi-layer structure including multiple layers of dielectric material, wherein the multi-layer structure includes one or more conductive pathways through the dielectric material;
a first die;
a second die, wherein the second die is between the first die and the multi-layer structure;
a third die, wherein the third die is between the first die and the multi-layer structure, and a plane parallel to a surface of the multi-layer structure extends through the second die and the third die; and
a fourth die, wherein the fourth die is attached to the multi-layer structure;
wherein:
the first die and the second die are attached by first interconnects,
the first die and the third die are attached by second interconnects, and
the third die includes through-substrate vias (TSVs) through a semiconductor substrate of the third die.
16. The microelectronic assembly of claim 15 , wherein the first interconnects have a pitch between 7 microns and 100 microns.
17. The microelectronic assembly of claim 15 , wherein the second interconnects have a pitch between 7 microns and 100 microns.
18. The microelectronic assembly of claim 15 , wherein the multi-layer structure includes one or more redistribution layers.
19. The microelectronic assembly of claim 15 , further comprising:
a fifth die between the third die and the multi-layer structure, wherein the fifth die is an inactive die.
20. The microelectronic assembly of claim 15 , further comprising:
a mold material between a portion of the first die and the multi-layer structure.
21. The microelectronic assembly of claim 15 , wherein the multi-layer structure includes a package substrate.
22. The microelectronic assembly of claim 15 , wherein a line from the first die to the multi-layer structure, perpendicular to a plane of the surface of the multi-layer structure, passes through the second die.
23. The microelectronic assembly of claim 15 , wherein a line from the first die to the multi-layer structure, perpendicular to a plane of the surface of the multi-layer structure, passes through the third die.
24. The microelectronic assembly of claim 15 , wherein the first interconnects include metal-to-metal interconnects.
25. The microelectronic assembly of claim 15 , wherein the second interconnects include metal-to-metal interconnects.
26. The microelectronic assembly of claim 15 , wherein the first die is attached to the second die without any dies in between.
27. The microelectronic assembly of claim 15 , wherein the first die is attached to the third die without any dies in between.
28. The microelectronic assembly of claim 15 , wherein the second die and the third die are spaced apart laterally.