Power and thermal management in a solid state drive

1. A solid state drive comprising:

controller circuitry to receive a command to perform an operation in the solid state drive from a host system communicatively coupled to the solid state drive;

a plurality of media channels, each media channel including a type of memory and a memory controller, the plurality of media channels including a block addressable non-volatile memory channel and a byte addressable write-in-place non-volatile media channel, the block addressable non-volatile memory channel including a block addressable non-volatile type of memory, the byte addressable write-in-place non-volatile media channel including a byte addressable write-in-place non-volatile type of memory; and

power management circuitry to monitor activity on the plurality of media channels to coordinate an active period and an idle period, using credits assigned to each of the plurality of media channels based on the type of memory included in each media channel, to manage a power budget for the solid state drive to perform the operation.

2. The solid state drive of claim 1 , wherein based on the activity on the plurality of media channels, the power management circuitry to move the power budget assigned to one of the plurality of media channels to another one of the plurality of media channels.

3. The solid state drive of claim 1 , wherein the controller circuitry to send a notification to the host system at start of the idle period to stop scheduling commands and to send another notification to the host system at end of the idle period to resume scheduling commands.

4. The solid state drive of claim 1 , wherein power is not provided to the plurality of media channels and the controller circuitry during the idle period.

5. The solid state drive of claim 1 , wherein the credits include available credits, the power management circuitry to enter the idle period while the available credits are less than a minimum threshold.

6. The solid state drive of claim 1 , wherein the power management circuitry to enter the idle period upon detection of a thermal event.

7. A method comprising:

receiving a command to perform an operation in a solid state drive from a host system communicatively coupled to the solid state drive;

monitoring activity on a plurality of media channels in the solid state drive, each media channel including a type of memory and a memory controller, the plurality of media channels including a block addressable non-volatile memory channel and a byte addressable write-in-place non-volatile media channel, the block addressable non-volatile memory channel including a block addressable non-volatile type of memory, the byte addressable write-in-place non-volatile media channel including a byte addressable write-in-place non-volatile type of memory; and

using credits assigned to each of the plurality of media channels based on the type of memory included in each media channel to coordinate an active period and an idle period to manage a power budget for the solid state drive to perform the operation.

8. The method of claim 7 , further comprising:

moving the power budget assigned to one of the plurality of media channels to another one of the plurality of media channels based on the activity on the plurality of media channels.

9. The method of claim 7 , further comprising:

sending a notification to the host system at start of the idle period to stop scheduling commands; and

sending another notification to the host system at end of the idle period to resume scheduling commands.

10. The method of claim 7 , wherein power is not provided to the plurality of media channels during the idle period.

11. The method of claim 7 , further comprising:

entering the idle period while available credits are less than a minimum threshold.

12. The method of claim 7 , further comprising:

entering the idle period upon detection of a thermal event.

13. A system comprising:

a processor;

a solid state drive communicatively coupled the processor, the solid state drive comprising:

controller circuitry to receive a command to perform an operation in the solid state drive from a host system communicatively coupled to the solid state drive;

a plurality of media channels, each media channel including a type of memory and a memory controller, the plurality of media channels including a block addressable non-volatile memory channel and a byte addressable write-in-place non-volatile media channel, the block addressable non-volatile memory channel including a block addressable non-volatile type of memory, the byte addressable write-in-place non-volatile media channel including a byte addressable write-in-place non-volatile type of memory; and

power management circuitry to monitor activity on the plurality of media channels to coordinate an active period and an idle period using credits assigned to each of the plurality of media channels based on the type of memory included in each media channel, to manage a power budget for the solid state drive to perform the operation.

14. The system of claim 13 , wherein based on the activity on the plurality of media channels, the power management circuitry to move the power budget assigned to one of the plurality of media channels to another one of the plurality of media channels.

15. The system of claim 13 , wherein power is not provided to the plurality of media channels and the controller circuitry during the idle period.

16. The system of claim 13 , wherein the credits include available credits, the power management circuitry to enter the idle period while the available credits are less than a minimum threshold.

17. The system of claim 13 , wherein the power management circuitry to enter the idle period upon detection of a thermal event.