Glitch detection in microelectronic devices, and related devices, systems, and methods
Glitch detection in microelectronic devices, and related methods, devices, and systems, are described herein. A device may detect and compare a number of pulses of a signal to a timing aperture to determine if any of the number of pulses is a glitch. The timing aperture, which may be based on a timing signal and/or one or more pulse width thresholds, may define an acceptable pulse versus a problematic glitch.
1. A device, comprising:
a pulse detector configured detect one or more pulses of a received signal; and
circuitry coupled to the pulse detector and configured to:
receive one or more captured signals from the pulse detector indicative of a width of the one or more pulses of the received signal;
compare the width of the one or more pulses of the received signal to a timing aperture defining a range of pulse widths; and
generate a signal indicative of a glitch in response to the width of the one or more pulses of the received signal being outside of the range of pulse widths of the timing aperture.
2. The device of claim 1 , wherein the circuitry is further configured to receive a timing signal that defines the timing aperture.
3. The device of claim 2 , wherein the pulse detector comprises:
a first edge detector configured to detect a first edge of the signal and generate a first captured signal of the one or more captured signals; and
a second edge detector configured to detect a second edge of the signal and generate a second captured signal of the one or more captured signals.
4. The device of claim 3 , wherein the circuitry comprises at least one filter configured to:
compare the first captured signal to a first portion of the timing signal;
compare the second captured signal to a second portion of the timing signal; and
generate the signal indicative of the glitch in response either the first captured signal or the second captured signal including the glitch.
5. The device of claim 3 , wherein the circuitry comprises:
a first filter configured to:
receive the first captured signal and the timing signal; and
generate a first indicator signal in response to the first captured signal rising and falling during a first portion of a true component of the timing signal; and
a second filter configured to:
receive the second captured signal and the timing signal; and
generate a second indicator signal in response to the second captured signal falling and rising during a second portion of the true component of the timing signal.
6. The device of claim 5 , further comprising logic coupled to an output of each of the first filter and the second filter, the logic configured to generate a glitch flag in response to receipt of the first indicator signal or the second indicator signal.
7. The device of claim 5 , wherein the circuitry further comprises:
a third filter configured to:
receive the first captured signal and the timing signal; and
generate a third indicator signal in response to the first captured signal rising and falling during a first portion of a complement component of the timing signal; and
a fourth filter configured to:
receive the second captured signal and the timing signal; and
generate a fourth indicator signal in response to the second captured signal falling and rising during a second portion of the complement component of the timing signal.
8. The device of claim 7 , further comprising logic coupled to an output of each of the first filter, the second filter, the third filter, and the fourth filter, the logic configured to generate a glitch flag in response to receipt of the first indicator signal, the second indicator signal, the third indicator signal, or the fourth indicator signal.
9. The device of claim 1 , wherein the circuitry is further configured to:
compare the width of the one or more pulses of the received signal to a first width threshold, a second width threshold, or both the first width threshold and the second width threshold; and
generate the signal indicative of the glitch in response to the width of the one or more pulses of the received signal being either less than the first width threshold or greater than the second width threshold.
10. A method, comprising:
detecting at least one pulse of a signal of a microelectronic device;
comparing a width of the at least one pulse of the signal to a predetermined timing aperture;
detecting a glitch based on the comparison of the width of the at least one pulse to the predetermined timing aperture; and
performing, via the microelectronic device, one or more operations in response to detection of the glitch.
11. The method of claim 10 , wherein detecting the glitch comprises detecting the glitch in response to the width of the at least one pulse of the signal being either greater than an upper pulse width threshold of the predetermined timing aperture or less than a lower pulse width threshold of the predetermined timing aperture.
12. The method of claim 10 , further comprising receiving a timing signal indicative of the predetermined timing aperture.
13. The method of claim 12 , wherein receiving the timing signal comprises receiving a pulse or a clock signal.
14. The method of claim 13 , wherein detecting the at least one pulse of the signal comprises capturing each of a positive-going pulse and a negative-going pulse of the signal.
15. The method of claim 14 , wherein comparing the width of the pulse of the signal to a predetermined timing aperture comprises:
comparing the positive-going pulse to a first portion of the timing signal; and
comparing the negative-going pulse to a second portion of the timing signal.
16. The method of claim 10 , wherein performing the one or more operations in response to detection of the glitch comprises performing the one or more operations in response to detection of the glitch and based on one or more mode register settings.
17. A system, comprising:
at least one input device;
at least one output device;
at least one processor device operably coupled to the input device and the output device; and
at least one memory system operably coupled to the at least one processor device, the memory system comprising:
a memory device, the memory device including:
a pulse detector configured detect a width of a number of pulses of a test signal; and
a filter coupled to the pulse detector and configured to:
receive a timing signal defining a timing period;
receive a signal indicative of the width of the number of pulses of the test signal;
compare the width of the number of pulses of the signal to the timing period to detect a glitch; and
generate a flag in response to detection of the glitch.
18. The system of claim 17 , wherein the pulse detector comprises a number of flip-flops, wherein each flip-flop of the number of flip-flops is configured to receive the test signal.
19. The system of claim 18 , wherein the filter comprises a number of AND gates, each AND gate of the number of AND gates configured to receive signals from two flip-flops of the number of flip-flops.
20. The system of claim 19 , further comprising an OR gate configured to receive an output from each AND gate of the number of AND gates.
21. The system of claim 17 , the memory device further comprising one or more mode registers, wherein one or more settings of the one or more mode registers is used to define one or more operations to be performed in response to detection of the glitch.