IP Library › Granted Patent US 12,066,945

Granted Patent B2

US 12,066,945 · App. 17/130,698 · Granted Aug 20, 2024

Dynamic shared cache partition for workload with large code footprint

Inventors: Prathmesh Kallurkar (Bangalore, IN); Anant Vithal Nori (Bangalore, IN); Sreenivas Subramoney (Bangalore, IN)

Assignee: Intel Corporation

G06F12/084 G06F9/5016 G06F12/0811 G06F12/0848 G06F12/0871

View Patent ↗

Loading inventors, assignments & file history…

Monitor This Case

Get email alerts when status or documents change.

Order Certified Copies

Most orders are placed with the USPTO same day — all within 24 business hours.

Order via The Patent Place →

Pre-filled with this patent's details

Quick Facts

Patent No.: US 12,066,945
App. No.: 17/130,698
Granted: Aug 20, 2024
Kind: B2

External Links

USPTO Patent Center↗ Full Patent PDF↗

Abstract

An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.

Claims (69)

1. An integrated circuit, comprising:

a core;

a first core cache memory at a first cache level, the first core cache memory coupled to the core;

a shared core cache memory at a second cache level, the shared core cache memory coupled to the core;

a first cache controller coupled to the core and communicatively coupled to the first core cache memory;

a second cache controller coupled to the core and communicatively coupled to the shared core cache memory; and

circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to:

determine if a workload has a large code footprint, comprising the circuitry to determine if, after a counted first number of misses at the first cache level exceeds a threshold, a counted second number of code misses at the first cache level exceeds a counted third number of data misses at the first cache level, and, if so determined,

partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero.

2. The integrated circuit of claim 1 , wherein the circuitry is further to:

count the second number of code misses at the first cache level from the workload; and

count the third number of data misses at the first cache level from the workload.

3. The integrated circuit of claim 2 , wherein the circuitry is further to:

reset the second number of code misses at the first cache level to be half of the counted second number of code misses at the first cache level after the counted first number of misses at the first cache level exceeds the threshold;

reset the third number of data misses at the first cache level to be half of the counted third number of data misses at the first cache level after the counted first number of misses at the first cache level exceeds the threshold; and

reset the first number of misses at the first cache level to zero after the counted first number of misses at the first cache level exceeds the threshold.

4. The integrated circuit of claim 1 , wherein the circuitry is further to:

restrict code cache lines from the workload to occupy the first chunk of ways for code for the workload; and

restrict data cache lines from the workload to occupy the second chunk of ways for data for the workload.

5. The integrated circuit of claim 4 , wherein the circuitry is further to:

decrease priority of non-hit cache lines in only the first chunk of ways for code in response to a demand hit to a cache line in the first chunk of ways for code; and

decrease priority of non-hit cache lines in only the second chunk of ways for data in response to a demand hit to a cache line in the second chunk of ways for data.

6. The integrated circuit of claim 4 , wherein the circuitry is further to:

evict a lowest priority cache line from only the first chunk of ways for code to insert a code cache line in the first chunk of ways for code; and

evict a lowest priority cache line from only the second chunk of ways for data to insert a data cache line in the second chunk of ways for data.

7. A method of controlling a cache, comprising:

determining if a workload has a large code footprint, comprising determining if, after a counted first number of misses at a first cache level exceeds a threshold, a counted second number of code misses at the first cache level exceeds a counted third number of data misses at the first cache level; and, if so determined,

partitioning N ways of a shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero, and wherein the shared core cache memory is at a second cache level.

8. The method of claim 7 , further comprising:

counting the second number of code misses at the first cache level from the workload; and

counting the third number of data misses at the first cache level from the workload.

9. The method of claim 8 , further comprising:

resetting the second number of code misses at the first cache level to be half of the counted second number of code misses at the first cache level after the counted first number of misses at the first cache level exceeds the threshold;

resetting the third number of data misses at the first cache level to be half of the counted third number of data misses at the first cache level after the counted first number of misses at the first cache level exceeds the threshold; and

resetting the first number of misses at the first cache level to zero after the counted first number of misses at the first cache level exceeds the threshold.

10. The method of claim 7 , further comprising:

restricting code cache lines from the workload to occupy the first chunk of ways for code for the workload; and

restricting data cache lines from the workload to occupy the second chunk of ways for data for the workload.

11. The method of claim 10 , further comprising:

decreasing priority of non-hit cache lines in only the first chunk of ways for code in response to a demand hit to a cache line in the first chunk of ways for code; and

decreasing priority of non-hit cache lines in only the second chunk of ways for data in response to a demand hit to a cache line in the second chunk of ways for data.

12. The method of claim 10 , further comprising:

evicting a lowest priority cache line from only the first chunk of ways for code to insert a code cache line in the first chunk of ways for code; and

evicting a lowest priority cache line from only the second chunk of ways for data to insert a data cache line in the second chunk of ways for data.

13. An apparatus, comprising:

one or more processor cores;

a first core cache memory at a first cache level;

a shared core cache memory at a second cache level;

a first cache controller communicatively coupled to the first core cache memory;

a second cache controller communicatively coupled to the shared core cache memory; and

circuitry communicatively coupled to the first cache controller and the second cache controller to:

14. The apparatus of claim 13 , wherein the circuitry is further to:

count the second number of code misses at the first cache level from the workload; and

count the third number of data misses at the first cache level from the workload.

15. The apparatus of claim 14 , wherein the circuitry is further to:

reset the first number of misses at the first cache level to zero after the counted first number of misses at the first cache level exceeds the threshold.

16. The apparatus of claim 13 , wherein the circuitry is further to:

restrict code cache lines from the workload to occupy the first chunk of ways for code for the workload; and

restrict data cache lines from the workload to occupy the second chunk of ways for data for the workload.

17. The apparatus of claim 16 , wherein the circuitry is further to:

decrease priority of non-hit cache lines in only the first chunk of ways for code in response to a demand hit to a cache line in the first chunk of ways for code; and

decrease priority of non-hit cache lines in only the second chunk of ways for data in response to a demand hit to a cache line in the second chunk of ways for data.

18. The apparatus of claim 16 , wherein the circuitry is further to:

evict a lowest priority cache line from only the first chunk of ways for code to insert a code cache line in the first chunk of ways for code; and

evict a lowest priority cache line from only the second chunk of ways for data to insert a data cache line in the second chunk of ways for data.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2020

From: KALLURKAR, PRATHMESH; NORI, ANANT VITHAL; SUBRAMONEY, SREENIVAS

To: INTEL CORPORATION

Reel/Frame 054732/0431 →

Continuity (1)

Related Publication 20220197794A1 · Jun 23, 2022