Doped gate dielectrics materials
A field effect transistor having at least a gate, source, and drain electrodes and a semiconductor channel for controlling transport of charge carriers between the source and drain electrodes, the gate being insulated from the channel by an dielectric, at least a portion of the dielectric disposed between the gate electrode and the semiconductor channel being doped or imbued with the an element which if doped or imbued into a semiconductor material would cause the semiconductor to be p-type. The p-type element used to dope or imbue the gate dielectric is preferably Mg.
1. A method of increasing a threshold voltage of an enhancement mode Gallium Nitride FET device having a gate dielectric material, the method comprising doping the gate dielectric material with an element which, if doped into a semiconductor material, would cause the semiconductor to be p-type and then annealing the device to have a threshold voltage greater than a positive 3 v.
2. The method of claim 1 wherein the element is Magnesium.
3. The method of claim 2 wherein at least a portion of the gate dielectric material is a Group III—nitride dielectric material.
4. The method of claim 3 wherein the Group III—nitride dielectric material is AlN.
5. The method of claim 4 wherein another portion of the gate dielectric material is SiN.
6. The method of claim 5 wherein the AlN and SiN form a two-layer dielectric stack with the AlN being in contact with an n-type Group III—nitride material drift layer and the SiN being in contact with a gate electrode of the enhancement mode Gallium Nitride FET device.
7. The method of claim 3 wherein the concentration of Magnesium in the Group III—nitride dielectric material is on the order of 2×10 18 cm −3 .
8. The method of claim 1 wherein the gate dielectric layer is formed from gas phase dielectric material components which are mixed with said p-type impurity prior to being disposed as the gate dielectric layer in the enhancement mode Gallium Nitride FET device.
9. The method of claim 8 wherein the p-type element is Magnesium.
10. The method of claim 9 wherein the gate dielectric material is a Group III—nitride dielectric material.
11. The method of claim 9 wherein the concentration of Magnesium in the Group III—nitride dielectric material is on the order of 2×10 18 cm −3 .
12. The method of claim 1 wherein the gate dielectric layer is activated by annealing to a temperature of at least 500° C. to thereby increase said threshold voltage of the enhancement mode Gallium Nitride FET device to be greater than said positive 3 v.
13. The method of claim 1 wherein the gate dielectric layer is activated by annealing to a temperature of at least 750° C. to thereby increase said threshold voltage of the enhancement mode Gallium Nitride FET device to be greater than said positive 3 v.
14. The method of claim 1 wherein the gate dielectric material is formed of at least two layers, a first layer of the gate dielectric material being AlN doped with said p-type element and the second layer being SiN.
15. The method of claim 14 wherein the AlN is disposed in contact with an n-type drift layer and the SiN is disposed in contact with a gate electrode of the enhancement mode Gallium Nitride FET device.
16. The method of claim 15 wherein the n-type drift layer is GaN doped with Si.
17. The method of claim 14 wherein the AlN is disposed in contact with a GaN channel layer and the SiN is disposed in contact with a gate electrode of the enhancement mode Gallium Nitride FET device.
18. The method of claim 1 therein the enhancement mode Gallium Nitride FET device is formed as an array of vertical field effect transistors, all formed at the same time and connected in common with each other, each field effect transistor in said array having a layer of said gate dielectric material.
19. The method of claim 18 whereon said array of vertical field effect transistors when viewed from a top-down orientation has a hexagonal layout.
20. A method of controlling a gate threshold voltage of an enhancement mode Gallium Nitride FET device without changing a physical layout of the enhancement mode Gallium Nitride FET device, the method comprising doping gate dielectric material in the enhancement mode Gallium Nitride FET device with Magnesium at a preselected concentration of the Magnesium in the gate dielectric material and annealing the enhancement mode Gallium Nitride FET device at a preselected temperature to activate the Magnesium in the gate dielectric material and thereby change the gate threshold voltage of the FET device to a voltage greater than a positive 3 v.
21. The method of claim 20 wherein the preselected concentration of Magnesium in the gate dielectric material is on the order of 2×10 18 cm −3 and the preselected temperature of the anneal is at least 500° C.