Energy-efficient core voltage selection apparatus and method
A processor core energy-efficiency core ranking scheme akin to a favored core in a multi-core processor system. The favored core is the energy-efficient core that allows an SoC to use the core with the lowest V min for energy-efficiency. Such V min values may be fused in appropriate registers or stored in NVM during HVM. An OS scheduler achieves optimal energy performance using the core ranking information to schedule certain applications on the core with lowest V min . A bootstrap flow identifies a bootstrap processor core (BSP) as the most energy efficiency core of the SoC and assigns that core the lowest APIC ID value according to the lowest V min . Upon reading the fuses or NVM, the microcode/BIOS calculates and ranks the cores. As such, microcode/BIOS calculates and ranks core APIC IDs based on efficiency around LFM frequencies. Based on the calculated and ranked cores, the microcode or BIOS transfers BSP ownership to the most efficiency core.
1. A non-transitory machine-readable storage media having machine-readable instructions that when executed cause one or more processors to perform a method comprising:
reading a minimum operation voltage (Vmin) per processor core in a multi-core system;
ranking, from a highest ranking to a lowest ranking, each processor core of the multi-core system according to the Vmin per processor core; and
modifying an existing bootstrap processor by assigning a new bootstrap processor to a processor core having the highest ranking.
2. The machine-readable storage media of claim 1 , wherein an operating system schedules interrupts or services low utilization tasks on the processor core having the highest ranking.
3. The machine-readable storage media of claim 1 , wherein the ranked processor cores have ranked identifications.
4. The machine-readable storage media of claim 3 having machine-readable instructions that when executed cause the one or more processors to perform the method comprising:
sharing ranked identifications of the processor cores to an operating system.
5. The machine-readable storage media of claim 4 , wherein the sharing of ranked identifications is via an Advanced Configuration and Power Interface table.
6. The machine-readable storage media of claim 5 , wherein the Advanced Configuration and Power Interface table comprises a Multiple APIC Description Table.
7. The machine-readable storage media of claim 1 , wherein ranking each processor core of the multi-core system is further based on efficiency of the processor core around low frequency mode frequencies.
8. The machine-readable storage media of claim 1 , wherein Vmin per processor core are stored in a non-volatile memory which is programmed during high-volume manufacturing with the Vmin per processor core.
9. A system-on-chip comprising:
a plurality of processor cores;
memory that stores minimum operating voltage (Vmin) per processor core from among the plurality of processor cores; and
a power management unit coupled to the processor cores, wherein the power management unit is to execute a firmware to:
rank each processor core according to the Vmin per processor core; and
assign a bootstrap processor to a processor core having a highest ranking.
10. The system-on-chip of claim 9 , wherein an operating system schedules interrupts or services low utilization tasks on the processor core having the highest ranking.
11. The system-on-chip of claim 9 , wherein the firmware is to assign ranked processor cores identifications.
12. The system-on-chip of claim 11 , wherein the firmware is to share the ranked identifications of the processor cores to an operating system.
13. The system-on-chip of claim 12 , wherein the firmware is to share the ranked identifications via an Advanced Configuration and Power Interface table.
14. The system-on-chip of claim 13 , wherein the Advanced Configuration and Power Interface table comprises a Multiple APIC Description Table.
15. The system-on-chip of claim 9 , wherein the firmware is to rank each processor core based on efficiency of the processor core around low frequency mode frequencies.
16. A system comprising:
a memory;
a processor coupled to the memory;
a wireless interface to allow the processor to communicate with another device, wherein the processor includes:
a plurality of processor cores, wherein the plurality of processor cores includes heterogenous process cores;
one or more memories that store a minimum operating voltage (Vmin) per processor core from among the plurality of processor cores; and
a power management unit coupled to the processor cores, wherein the power management unit is to execute a firmware to:
rank each processor core with an identification according to the Vmin per processor core; and
transfer ownership a bootstrap processor to a processor core having a highest ranking.
17. The system of claim 16 , wherein an operating system schedules interrupts or services low utilization tasks on the processor core having the highest ranking.
18. The system of claim 16 , wherein the firmware is to share the ranked identifications of the processor cores to an operating system.
19. The system of claim 16 , wherein the firmware is to rank each processor core based on efficiency of the processor core around low frequency mode frequencies.
20. The system of claim 16 , wherein the firmware is to share the ranked identifications via an Advanced Configuration and Power Interface table which comprises a Multiple APIC Description Table.