JFET with implant isolation
A vertical junction field effect transistor (JFET) includes a substrate, an active region having a plurality of semiconductor fins, a source metal layer on an upper surface of the fins, a source metal pad layer coupled to the semiconductor fins through the source metal layer, a gate region surrounding the semiconductor fins, and a body diode surrounding the gate region.
1. A vertical junction field effect transistor (JFET), comprising:
a substrate;
an active region comprising a plurality of semiconductor fins;
a source metal layer electrically coupled to a surface of the semiconductor fins;
a source metal pad layer coupled to the semiconductor fins through the source metal layer;
a gate region surrounding the semiconductor fins; and
a body diode surrounding the gate region.
2. The vertical JFET of claim 1 , further comprising an isolation region disposed between the active region and the body diode.
3. The vertical JFET of claim 2 , wherein the isolation region comprises a trench.
4. The vertical JFET of claim 2 , wherein the isolation region comprises a floating fin not electrically coupled to the source pad metal layer.
5. The vertical JFET of claim 2 , wherein the isolation region comprises an n-type doped region.
6. The vertical JFET of claim 1 , wherein the body diode comprises an anode coupled to the source metal layer and a cathode coupled to a drain of the JFET.
7. The vertical JFET of claim 1 , further comprising a drift region coupled to the substrate, wherein the plurality of semiconductor fins are coupled to the drift region.
8. The vertical JFET of claim 7 , wherein
the substrate comprises an n+ GaN layer;
the drift region comprise an n− GaN layer;
the semiconductor fins comprise an n GaN layer;
the body diode comprises an anode on the drift region and a cathode formed by the drift region, wherein the anode comprises a p GaN layer and is coupled to the source metal layer, and wherein the cathode is coupled to a drain of the JFET; and
the vertical JFET further comprising an edge termination region comprising the p GaN layer and surrounding the body diode.
9. The vertical JFET of claim 1 , wherein the body diode is one of a PN junction diode, a Schottky diode, or a merged P-i-N Schottky (MPS) diode.
10. The vertical JFET of claim 1 , further comprising an edge termination region surrounding the body diode.
11. A semiconductor device, comprising:
a substrate comprising an n+ GaN layer;
a drift layer coupled to the substrate and comprising an n− GaN layer;
a plurality of fins comprising an n GaN material and coupled to the drift layer;
a gate layer comprising a p GaN material and surrounding the plurality of fins;
an integrated body diode surrounding the plurality of fins; and
an isolation region disposed between the plurality of fins and the integrated body diode.
12. The semiconductor device of claim 11 , wherein the integrated body diode is one of a PN diode, a Schottky diode, or a merged PIN Schottky diode.
13. The semiconductor device of claim 11 , wherein the isolation region comprises one of a trench, a floating fin, or an n-type doped region.
14. The semiconductor device of claim 11 , further comprising a metal layer electrically coupled to the plurality of fins.
15. The semiconductor device of claim 14 , wherein the integrated body diode comprises an anode coupled to the metal layer.
16. The semiconductor device of claim 11 , wherein the semiconductor device further includes an edge termination region surrounding the integrated body diode.