IP Library Granted Patent US 12,112,178
Granted Patent B2
US 12,112,178 · App. 17/134,322 · Granted Oct 8, 2024

Memory-independent and scalable state component initialization for a processor

Inventors: Abhimanyu Kanaiya Varde (Portland, OR); Karuna Ramkumar (Hillsboro, OR); Robert Valentine (Kiryat Tivon, IL)
Assignee: Intel Corporation
G06F9/44505G06F9/30098G06F9/30145
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Quick Facts
Patent No.
US 12,112,178
App. No.
17/134,322
Granted
Oct 8, 2024
Kind
B2
Abstract

Systems or methods of the present disclosure may provide an initialization technique that enables the initialization of multiple states in an efficient manner. The initialization technique includes a register to track usage of state components of the processor and a decode unit to decode a state initialization instruction. The state initialization instruction indicates that of the state components are to be initialized. The initialization technique also includes an execution unit coupled with the decode unit. The execution unit, in response to the state initialization instruction, is to initialize the state components without reading another state component from memory as part of the initialization.

Claims (40)

1. A processor comprising:

a register to track usage of state components of the processor;

a decode unit to:

decode a state initialization instruction, wherein the state initialization instruction indicates that the state components are to be initialized by zeroing out the state components; and

determine whether a current privilege exceeds a privilege threshold and set a bit mask based at least in part on the current privilege exceeding the privilege threshold; and

an execution unit coupled with the decode unit, wherein the execution unit, in response to the state initialization instruction, is to initialize the state components based on the bit mask and without reading another state component from memory as part of the initialization.

2. The processor of claim 1 , wherein the execution unit, in response to the state initialization instruction, does not initialize the another state component as part of the initializing the state components.

3. The processor of claim 1 , wherein the execution unit, in response to the state initialization instruction, does not use state-specific instruction sets for the state components to perform the initialization.

4. The processor of claim 1 , wherein the execution unit does not perform a restore instruction to complete the initialization.

5. The processor of claim 1 , wherein initializing the state components by the execution unit comprises:

determining that a state component of the state components is in use by checking an in-use flag for the state component; and

in response to determining that the state component is in use, setting an initialization flag indicating that the state component is to be initialized.

6. The processor of claim 5 , wherein initializing comprises, after initialization:

determining that the state component has been initialized; and

in response to the determination that the state component has been initialized, clearing an in-use flag for the state component.

7. The processor of claim 1 , wherein initializing comprises initializing the state components without accessing memory to read any contents of any stored state components.

8. A method comprising:

determining that a plurality of state components for a processor is to be initialized by zeroing out the state components;

determining whether a current privilege exceeds a privilege threshold;

storing indications of the plurality of state components in a bit mask, wherein storing the indications in the bit mask for a first set of state components is based at least in part on whether the current privilege exceeds the privilege threshold;

determining whether the plurality of state components are in use;

for the plurality of state components that are in use, marking the respective state component as to be initialized based at least in part on an in-use condition of the respective state component; and

initializing the state components in the bit mask based at least in part on the to-be-initialized marking.

9. The method of claim 8 , wherein determining that the plurality of state components comprises setting the bit mask for a second set of state components based on the current privilege not exceeding the privilege threshold.

10. The method of claim 9 , wherein the first set of state components comprises global use supervisor states, and the second set of state components does not.

11. The method of claim 8 , wherein the in-use condition indicates that the respective state component has changed from an initialization state.

12. The method of claim 11 comprising determining the in-use condition indicates that the respective state contains a value other than zero.

13. The method of claim 11 comprising clearing at least a portion of an in-use bitmap indicating the in-use condition once the respective state is initialized.

14. A system to process instructions comprising:

a register to track usage of state components of the system;

a decode unit to decode a state initialization instruction, wherein the state initialization instruction indicates that one or more of the state components are to be initialized by zeroing out the state components; and

an execution unit coupled with the decode unit, wherein the execution unit, in response to the state initialization instruction, is to:

set a bit mask for the one or more state components, wherein setting the bit mask is based at least in part on a current privilege level in use in the system;

determine whether the one or more state components have changed from an initialized state based at least in part on in-use bitmap used to track the status of respective state components of the one or more state components;

for the one or more state components that have changed from the initialized state, set initialize flags for the one or more state components;

initialize the one or more state components that have set initialize flags; and

clear the in-use state components for the initialized state components.

15. The system of claim 14 , wherein the register comprises a requested-feature bitmap.

16. The system of claim 15 , wherein the requested-feature bitmap is set using a logical AND of one or more registers corresponding to global user and supervisor states when a current privilege level is above a threshold.

17. The system of claim 16 , wherein the requested-feature bitmap is set using a logical AND of the one or more registers corresponding to global user states when the current privilege level is below a threshold.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 15, 2026
From: INTEL CORPORATION
To: INTEL PRODUCTS IP LLC
Reel/Frame 076025/0681 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 17, 2021
From: VARDE, ABHIMANYU KANAIYA; RAMKUMAR, KARUNA; VALENTINE, ROBERT
To: INTEL CORPORATION
Reel/Frame 056263/0788 →
Continuity (1)
Related Publication 20220206825A1 · Jun 30, 2022