Instructions to convert from FP16 to BF8
Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.
1. An apparatus comprising:
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
a processor coupled to the plurality of memory controllers, and coupled to the L2 cache memory, the processor having a plurality of cores and a plurality of levels of cache memory, the cores including circuitry to perform operations corresponding to an instruction, the instruction to identify a source register that is to include a plurality of half-precision floating-point data elements and to identify a destination register, wherein the half-precision floating-point data elements are 16-bit data elements, the operations including to:
convert the plurality of half-precision floating-point data elements to a plurality of corresponding 8-bit floating-point data elements, wherein, when one or more of the half-precision floating-point data elements are normal numbers, conversion of the one or more normal numbers to one or more corresponding 8-bit floating-point data elements is to be performed according to a round to nearest even rounding mode, and the one or more corresponding 8-bit floating-point data elements are each to include one sign bit, five exponent bits, and two mantissa bits, wherein for each normal half-precision floating-point data element, a corresponding 8-bit floating-point data element is to be converted from the half-precision floating point data element using a rounding bias; and
store the plurality of 8-bit floating-point data elements in the destination register;
an interconnect interface coupled to the processor; and
a bus controller interface coupled to the processor.
2. The apparatus of claim 1 , wherein the instruction allows only the round to nearest even rounding mode for the conversion of the one or more normal numbers to the one or more corresponding 8-bit floating-point data elements.
3. The apparatus of claim 1 , wherein the cores comprise graphics cores.
4. The apparatus of claim 1 , wherein the cores comprise heterogeneous cores.
5. The apparatus of claim 1 , wherein the cores comprise heterogeneous graphics cores.
6. The apparatus of claim 1 , further comprising an instruction converter to convert the instruction into one or more instructions of a different instruction set executable by the cores.
7. The apparatus of claim 1 , wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include setting a most significant bit of a mantissa of each of one or more corresponding 8-bit floating-point data elements.
8. The apparatus of claim 1 , wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include modifying a bit of a mantissa of each of one or more corresponding 8-bit floating-point data elements.
9. The apparatus of claim 1 , wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include forcing quiet NAN (QNAN) for each of one or more corresponding 8-bit floating-point data elements.
10. An apparatus comprising:
circuitry to receive an instruction, the instruction to identify a source register that is to include a plurality of half-precision floating-point data elements and to identify a destination register, wherein the half-precision floating-point data elements are 16-bit data elements;
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
execution circuitry to perform operations corresponding to the instruction, including to:
convert the plurality of half-precision floating-point data elements to a plurality of corresponding 8-bit floating-point data elements, wherein, when one or more of the half-precision floating-point data elements are normal numbers, conversion of the one or more normal numbers to one or more corresponding 8-bit floating-point data elements is to be performed according to a round to nearest even rounding mode, and the one or more corresponding 8-bit floating-point data elements are each to include one sign bit, five exponent bits, and two mantissa bits, wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include truncating a most significant 8 bits of the half-precision floating-point data element and setting a most significant bit of a mantissa of each of one or more corresponding 8-bit floating-point data elements, wherein for each normal half-precision floating-point data element, a corresponding 8-bit floating-point data element is to be converted from the half-precision floating point data element using a rounding bias; and
store the plurality of 8-bit floating-point data elements in the destination register;
an interconnect interface coupled to the execution circuitry; and
a bus controller interface coupled to the execution circuitry.
11. The apparatus of claim 10 , wherein the instruction allows only the round to nearest even rounding mode for the conversion of the one or more normal numbers to the one or more corresponding 8-bit floating-point data elements.
12. The apparatus of claim 10 , wherein the execution circuitry is within a graphics core.
13. The apparatus of claim 10 , further comprising an instruction converter to convert the instruction into one or more instructions of a different instruction set executable by the execution circuitry.
14. An apparatus comprising:
an instruction converter to convert a first instruction into one or more other instructions, the first instruction to identify a source register that is to include a plurality of half-precision floating-point data elements and to identify a destination register, wherein the half-precision floating-point data elements are 16-bit data elements;
a plurality of memory controllers;
a level-two (L2) cache memory coupled to the plurality of memory controllers;
execution circuitry to perform operations corresponding to the first instruction, including to:
convert the plurality of half-precision floating-point data elements to a plurality of corresponding 8-bit floating-point data elements, wherein, when one or more of the half-precision floating-point data elements are normal numbers, conversion of the one or more normal numbers to one or more corresponding 8-bit floating-point data elements is to be performed according to a round to nearest even rounding mode, and the one or more corresponding 8-bit floating-point data elements are each to include one sign bit, five exponent bits, and two mantissa bits, wherein for each normal half-precision floating-point data element, a corresponding 8-bit floating-point data element is to be converted from the half-precision floating point data element using a rounding bias; and
store the plurality of 8-bit floating-point data elements in the destination register;
an interconnect interface coupled to the execution circuitry; and
a bus controller interface coupled to the execution circuitry.
15. The apparatus of claim 14 , wherein the first instruction allows only the round to nearest even rounding mode for the conversion of the one or more normal numbers to the one or more corresponding 8-bit floating-point data elements.
16. The apparatus of claim 14 , wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include modifying a bit of a mantissa of each of one or more corresponding 8-bit floating-point data elements.
17. The apparatus of claim 14 , wherein, when one or more of the half-precision floating-point data elements are not-a-number (NaN) data elements, conversion of the one or more NaN data elements is to include forcing quiet NAN (QNAN) for each of one or more corresponding 8-bit floating-point data elements.
18. The apparatus of claim 14 , wherein the execution circuitry is part of a graphics core.